Functional testing of HDL specifications is one of the most promising approaches for the verification of the functionalities of a design before synthesis. The contribution of this work is the development of a test generation algorithm targeting a new coverage metric (called bit-coverage) that provides full statement coverage, branch coverage, condition coverage and partial path coverage for behaviorally sequential models. The behavioral test sequences can be also the only way to evaluate testability of VHDL model for which a gate-level representation is not available (e.g third-party cores), since the behavioral error model is characterized also by a high correlation with the RT and gate-level stuck-at fault model. Moreover the preciseness of the proposed coverage metric makes the identified test sequences more effective in identifying design errors, than other test patterns developed by following standard coverage metrics

Functional Test Generation for Behaviorally Sequential Models

FERRANDI, FABRIZIO;SCIUTO, DONATELLA
2001-01-01

Abstract

Functional testing of HDL specifications is one of the most promising approaches for the verification of the functionalities of a design before synthesis. The contribution of this work is the development of a test generation algorithm targeting a new coverage metric (called bit-coverage) that provides full statement coverage, branch coverage, condition coverage and partial path coverage for behaviorally sequential models. The behavioral test sequences can be also the only way to evaluate testability of VHDL model for which a gate-level representation is not available (e.g third-party cores), since the behavioral error model is characterized also by a high correlation with the RT and gate-level stuck-at fault model. Moreover the preciseness of the proposed coverage metric makes the identified test sequences more effective in identifying design errors, than other test patterns developed by following standard coverage metrics
2001
Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
automatic test pattern generation,formal verification,high level synthesis,logic testing,sequential circuits,ATPG,HDL specifications,RTL faults,VHDL model testability evaluation,behavioral error model,behavioral test sequences,behaviorally sequential models,bit-coverage,branch coverage,condition coverage,coverage metric,design error identification,full statement coverage,functional test generation,functional testing,partial path coverage,test generation algorithm,Computer bugs,Costs,Emulation,Hardware design languages,Marine vehicles,Process design,Product development,Sequential analysis,Software testing,Standards development
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/249633
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