This paper addresses the problem of test vectors generation starting from an high level description of the system under test, specified in SystemC. The verification method considered is based upon the simulation of input sequences. The system model adopted is the classical Finite State Machine model. Then, according to different strategies, a set of sequences can be obtained, where a sequence is an ordered set of transitions. For each of these sequences, a set of constraints is extracted. Test sequences can be obtained by generating and solving the constraints, by using a constraint solver (GProlog). A solution of the constraint solver yields the values, of the input signals for which a sequence of transitions in the FSM is executed. If the constraints cannot be solved, it implies that the corresponding sequence cannot be executed by any test. The presented algorithm is not based on a specific fault model, but aims at reaching the highest possible path coverage

Functional verification for SystemC descriptions using constraint solving

FERRANDI, FABRIZIO;SCIUTO, DONATELLA
2002-01-01

Abstract

This paper addresses the problem of test vectors generation starting from an high level description of the system under test, specified in SystemC. The verification method considered is based upon the simulation of input sequences. The system model adopted is the classical Finite State Machine model. Then, according to different strategies, a set of sequences can be obtained, where a sequence is an ordered set of transitions. For each of these sequences, a set of constraints is extracted. Test sequences can be obtained by generating and solving the constraints, by using a constraint solver (GProlog). A solution of the constraint solver yields the values, of the input signals for which a sequence of transitions in the FSM is executed. If the constraints cannot be solved, it implies that the corresponding sequence cannot be executed by any test. The presented algorithm is not based on a specific fault model, but aims at reaching the highest possible path coverage
2002
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
automatic test pattern generation;binary sequences;circuit simulation;constraint handling;finite state machines;formal specification;formal verification;hardware description languages;ATPG;FSM system model;GProlog;SystemC descriptions;constraint solving;finite state machine model;functional verification;high level description;input sequences simulation;path coverage;test sequences;test vectors generation;Automata;Automatic test pattern generation;Automatic testing;Computational modeling;Data structures;Electronic switching systems;Genetic algorithms;Hardware design languages;System testing;Test pattern generators
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/270034
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