RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

SCIUTO, DONATELLA
 Distribuzione geografica
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Continente #
NA - Nord America 29.300
EU - Europa 8.614
AS - Asia 3.031
SA - Sud America 430
AF - Africa 94
OC - Oceania 25
Continente sconosciuto - Info sul continente non disponibili 17
Totale 41.511
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Nazione #
US - Stati Uniti d'America 28.850
IT - Italia 2.330
SG - Singapore 1.331
UA - Ucraina 1.252
SE - Svezia 1.045
DE - Germania 839
VN - Vietnam 731
FI - Finlandia 676
GB - Regno Unito 601
AT - Austria 593
CN - Cina 450
CA - Canada 425
IE - Irlanda 382
BR - Brasile 362
ES - Italia 219
NL - Olanda 151
CH - Svizzera 126
FR - Francia 100
JO - Giordania 98
IN - India 74
BE - Belgio 73
PL - Polonia 63
ID - Indonesia 56
KR - Corea 55
TR - Turchia 51
CI - Costa d'Avorio 43
RU - Federazione Russa 32
HK - Hong Kong 31
RO - Romania 26
AR - Argentina 21
JP - Giappone 21
AU - Australia 19
EU - Europa 16
GR - Grecia 14
CZ - Repubblica Ceca 13
IQ - Iraq 13
BD - Bangladesh 12
PK - Pakistan 12
AE - Emirati Arabi Uniti 11
EC - Ecuador 11
BJ - Benin 10
MX - Messico 10
PT - Portogallo 10
MA - Marocco 9
TW - Taiwan 9
VE - Venezuela 9
EE - Estonia 8
IR - Iran 8
KG - Kirghizistan 8
LU - Lussemburgo 8
PH - Filippine 8
AM - Armenia 7
AZ - Azerbaigian 7
CO - Colombia 7
DK - Danimarca 7
MU - Mauritius 7
IL - Israele 6
LV - Lettonia 6
PY - Paraguay 6
KZ - Kazakistan 5
NZ - Nuova Zelanda 5
PE - Perù 5
RS - Serbia 5
SK - Slovacchia (Repubblica Slovacca) 5
ZA - Sudafrica 5
AL - Albania 4
BG - Bulgaria 4
CR - Costa Rica 4
DZ - Algeria 4
JM - Giamaica 4
KE - Kenya 4
MY - Malesia 4
NO - Norvegia 4
NP - Nepal 4
SM - San Marino 4
UZ - Uzbekistan 4
BO - Bolivia 3
BY - Bielorussia 3
CL - Cile 3
HR - Croazia 3
LK - Sri Lanka 3
LT - Lituania 3
PA - Panama 3
SC - Seychelles 3
UY - Uruguay 3
BA - Bosnia-Erzegovina 2
CY - Cipro 2
DO - Repubblica Dominicana 2
EG - Egitto 2
GE - Georgia 2
KH - Cambogia 2
SN - Senegal 2
TG - Togo 2
YE - Yemen 2
AF - Afghanistan, Repubblica islamica di 1
AO - Angola 1
HU - Ungheria 1
IS - Islanda 1
LB - Libano 1
MK - Macedonia 1
Totale 41.503
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Città #
Fairfield 4.290
Woodbridge 3.267
Houston 2.385
Chandler 2.145
Ashburn 2.072
Wilmington 1.829
Ann Arbor 1.827
Seattle 1.741
Cambridge 1.457
Santa Clara 925
Jacksonville 761
Dearborn 604
Milan 598
Singapore 594
Vienna 578
Boardman 563
Council Bluffs 466
Lawrence 462
Dong Ket 420
Dublin 376
Medford 374
Ottawa 372
San Diego 249
Beijing 224
Des Moines 220
Helsinki 217
Málaga 209
Bern 105
Auburn Hills 100
Princeton 99
Amman 98
Amsterdam 90
New York 73
London 71
The Dalles 70
Brussels 67
Jakarta 54
Los Angeles 54
Redwood City 52
Rome 52
Washington 51
Warsaw 47
Mountain View 46
Abidjan 43
Istanbul 41
Norwalk 41
Shanghai 32
Frankfurt am Main 31
Verona 31
São Paulo 30
Seongnam 29
Columbus 26
Naples 24
Busto Arsizio 22
Hong Kong 21
Hefei 19
Miami 19
Baie-D'Urfe 18
Florence 18
Indiana 18
Guangzhou 17
Redmond 17
Nanjing 16
Turin 16
Munich 15
Phoenix 15
Bologna 13
Bresso 13
Falkenstein 13
Kunming 13
Atlanta 12
Chicago 12
Hounslow 12
Nuremberg 12
Saronno 12
Buffalo 11
Falls Church 11
Modena 11
Padova 11
Parma 11
Rio de Janeiro 11
Cotonou 10
Lappeenranta 10
Olgiate Comasco 10
Palermo 10
Seoul 10
Brescia 9
Duncan 9
Kumar 9
Manaus 9
Reston 9
San Donato Milanese 9
Zurich 9
Bari 8
Bishkek 8
Groningen 8
Kassel 8
Kilburn 8
Monza 8
New Bedfont 8
Totale 31.260
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Nome #
Tecnologie di recupero e separazione di terre rare: stato dell’arte e prospettive 337
Optimization strategies in design space exploration 253
Alfa Romeo technical office; Architettura della città; Casabella; Enios; House in Milan; Ina-casa programme; Nostra signora della misericordia; Palazzo bianco/Palazzo rosso; Rational architecture; Triennale di Milano; Velasca tower;Zentrum Paul Klee 189
A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA 186
A Performance-Aware Quality of Service-Driven Scheduler for Multicore Processors 175
Array partitioning: a methodology for reconfigurability and reconfiguration problems 173
An Evolutionary Approach to Area-Time Optimization of FPGA designs 169
Efficient Hardware Design of Iterative Stencil Loops 162
Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering 153
The Case for Polymorphic Registers in Dataflow Computing 151
A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems 151
Adaptive and Flexible Smartphone Power Modeling 147
A Design Methodology for the Exploitation of High Level Communication Synthesis 145
Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs 145
A CMOS fault tolerant architecture for switch-level faults 144
A multiprocessor self-reconfigurable jpeg2000 encoder 144
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 143
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis 143
Reliability Properties Assessment at System Level: A Co-design Framework 141
D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems 139
An Approach to Functional Testing of VLIW Architectures 139
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs 138
The FASTER vision for designing dynamically reconfigurable systems 135
A Unified Approach to Canonical Form-based Boolean Matching 133
Extensions of the hArtes Tool Chain 132
Reliable System Co-Design: the FIR Case Study 131
Lightweight DMA management mechanisms for multiprocessors on FPGA 129
cODA: An Open-Source Framework to Easily Design Context-Aware Android Apps 128
On the Evolution of Hardware Circuits via Reconfigurable Architectures 127
Towards a Performance-as-a-Service Cloud 127
SMASH: A Heuristic Methodology for Designing Partially Reconfigurable MPSoCs 126
A Compact Transactional Memory Multiprocessor System on FPGA 126
A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip 125
null 124
MPower: towards an adaptive power management system for mobile devices 124
A design methodology to implement memory accesses in High-Level Synthesis 123
Model-Based Design for Wireless Body Sensor Network Nodes 123
Occupancy Detection via iBeacon on Android Devices for Smart Building Management 123
A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms 122
Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA 122
Self Reconfigurable Implementation of the JPEG Encoder 122
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 122
Morphone.OS: Context-awareness in everyday life 122
Automatic parallelization of sequential specifications for symmetric MPSoCs 122
Experimental evaluation and modeling of thermal phenomena on mobile devices 122
A Design Framework to Efficiently Explore Energy-Delay Tradeoffs 121
A2B: an Integrated Framework for Designing Heterogeneous and Reconfigurable Systems 121
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance 121
Analog circuits placement: A constraint driven methodology 121
Automated Fine-Grained CPU Provisioning for Virtual Machines 120
Functional Test Generation for Behaviorally Sequential Models 120
An instruction-level methodology for power estimation and optimization of embedded VLIW cores 119
A new switching-level approach to multiple-output functions synthesis 119
HERA Project's Holistic Evolutionary Framework 119
B2IRS: A Technique to Reduce BAN-BAN Interferences in Wireless Sensor Networks 118
On Self-adaptive Resource Allocation through Reinforcement Learning 118
Reliable System Specification for Self-Checking Data-Paths 117
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors 117
A Design Flow Tailored for Self Dynamic Reconfigurable Architecture 117
Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor Networks 117
Application of a testing framework to VHDL descriptions at different abstraction levels 117
A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices 117
ReBit: A Tool to Manage and Analyse FPGA-Based Reconfigurable Systems 117
System Level Hardware--Software Design Exploration with XCS 117
FIDA: A framework to automatically integrate FPGA kernels within data-science applications 117
A Power-Efficient Methodology for Mapping Applications on Multi-Processor System-on-Chip Architectures 117
HERA: Hardware evolution over reconfigurable architectures 117
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 116
Concurrency Emulation and Analysis of Parallel Applications for Multi-Processor System-on-Chip Co-Design 115
A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture 115
An Interrupt Controller for FPGA-based Multiprocessors 115
OpenMPower: An Open and Accessible Database About Real World Mobile Devices 115
An Efficient Heuristic Approach to Solve the Unate Covering Problem 114
Exploiting TLM and Object Introspection for System-Level Simulation 113
TaBit: A framework for task graph to bitstream generation 113
A dual-priority real-time multiprocessor system on FPGA for automotive applications 113
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 113
Construction Techniques for Systematic SEC-DED Codes with Single Byte Error Detection and Partial Correction Capability for Computer Memory Systems 113
Combined software and hardware techniques for the design of reliable IP processors 112
Coloring the Cloud for Predictable Performance 112
A model of soft error effects in generic IP processors 112
A Scalable FPGA Design for Cloud N-Body Simulation 112
Design of VHDL based Totally Self-Checking Finite State machine and Data Path descriptions 112
Dataflow Computing with Polymorphic Registers 111
Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics 111
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 111
DOMINANCE BASED METHODOLOGIES FOR MULTIPLE-OUTPUT CMOS COMBINATIONAL GATES SYNTHESIS 111
The Shining embedded system design methodology based on self dynamic reconfigurable architectures 111
Factors Affecting ERP System Adoption: a Comparative Analysis between SMEs and Large Companies 110
An Architecture for Dynamically Reconfigurable Real Time Audio Processing Systems 110
Danger-system: Exploring new ways to manage occupants safety in smart building 110
An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems 110
hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms 109
Affinity-driven system design exploration for heterogeneous multiprocessor SoC 109
A Novel SoC Design Methodology Combining Adaptive Software and Reconfigurable Hardware 109
A Multi-Level Strategy for Software Power Estimation 108
The Design of Reliable Devices for Mission Critical Applications 108
Sink state analysis in multi-tenant smart buildings 108
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops 108
An Application-centered Design Flow for Self Reconfigurable Systems Implementation 107
Totale 12.837
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Categoria #
all - tutte 137.028
article - articoli 29.274
book - libri 1.657
conference - conferenze 97.672
curatela - curatele 264
other - altro 0
patent - brevetti 1.230
selected - selezionate 0
volume - volumi 6.827
Totale 273.952
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20202.732 0 0 0 0 0 0 0 0 1.135 464 862 271
2020/20215.113 490 234 526 255 362 290 358 515 358 498 347 880
2021/20224.249 162 602 341 158 565 171 248 203 205 225 530 839
2022/20235.027 614 412 125 544 599 674 50 338 730 322 348 271
2023/20242.350 194 486 185 214 161 260 114 230 16 164 51 275
2024/20254.656 135 141 270 192 1.295 564 383 842 834 0 0 0
Totale 42.090