| Nome |
# |
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Occupancy Detection via iBeacon on Android Devices for Smart Building Management, file e0c31c08-57b7-4599-e053-1705fe0aef77
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1.021
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FPGA-based Embedded System Implementation of Audio Signal Alignment, file e0c31c0f-c643-4599-e053-1705fe0aef77
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571
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Pushing the Level of Abstraction of Digital System Design: a Survey on How to Program FPGAs, file e3b8d0bb-125b-4457-9780-250f72ef7a02
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534
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A Framework for Customizable FPGA-based Image Registration Accelerators, file e0c31c11-0e69-4599-e053-1705fe0aef77
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455
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Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems, file e0c31c09-2d2b-4599-e053-1705fe0aef77
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453
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Enabling Transparent Hardware Acceleration on Zynq SoC for Scientific Computing, file e0c31c0f-da82-4599-e053-1705fe0aef77
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411
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On how to design smart energy-efficient buildings, file e0c31c08-57b6-4599-e053-1705fe0aef77
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382
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BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems, file e0c31c0f-ba41-4599-e053-1705fe0aef77
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362
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On how to accelerate iterative stencil loops: A scalable streaming-based approach, file e0c31c0e-be75-4599-e053-1705fe0aef77
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330
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On Power and Energy Consumption Modeling for Smart Mobile Devices, file e0c31c08-77b6-4599-e053-1705fe0aef77
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303
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Danger-system: Exploring new ways to manage occupants safety in smart building, file e0c31c09-6d75-4599-e053-1705fe0aef77
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303
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Building High-Performance, Easy-to-use Polymorphic Parallel Memories with HLS, file e0c31c0f-c63b-4599-e053-1705fe0aef77
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302
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Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance, file e0c31c0a-0bf9-4599-e053-1705fe0aef77
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298
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Automatic parallelization of sequential specifications for symmetric MPSoCs, file e0c31c09-1b51-4599-e053-1705fe0aef77
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294
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hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms, file e0c31c09-e1d0-4599-e053-1705fe0aef77
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292
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Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs Distributed Systems, file e0c31c0f-c48e-4599-e053-1705fe0aef77
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255
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Faber: a Hardware/Software Toolchain for Image Registration, file b7a401ca-75bd-4e7c-b559-226c48080583
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251
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A Comprehensive Methodology to Optimize FPGA Designs via the Roofline Model, file e0c31c12-3ea4-4599-e053-1705fe0aef77
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247
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cODA: An Open-Source Framework to Easily Design Context-Aware Android Apps, file e0c31c08-634d-4599-e053-1705fe0aef77
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229
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K-Ways Partitioning of Polyhedral Process Networks: A Multi-level Approach, file e0c31c09-6d79-4599-e053-1705fe0aef77
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211
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FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration, file e0c31c09-6dba-4599-e053-1705fe0aef77
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207
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Protecting Hardware IP Cores During High-Level Synthesis, file e0c31c12-3d16-4599-e053-1705fe0aef77
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207
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In Car Audio, file e0c31c09-cb16-4599-e053-1705fe0aef77
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188
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OpenMPower: An Open and Accessible Database About Real World Mobile Devices, file e0c31c08-77b4-4599-e053-1705fe0aef77
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179
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The Case for Polymorphic Registers in Dataflow Computing, file e0c31c0a-cf8e-4599-e053-1705fe0aef77
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176
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A Performance-Aware Quality of Service-Driven Scheduler for Multicore Processors, file e0c31c08-9496-4599-e053-1705fe0aef77
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175
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Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems, file e0c31c09-6d76-4599-e053-1705fe0aef77
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157
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Design Methodologies for Reconfigurable NoC-based Embedded Systems, file e0c31c08-db65-4599-e053-1705fe0aef77
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156
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Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs, file e0c31c09-2e6d-4599-e053-1705fe0aef77
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149
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BuildingRules: A Trigger-Action Based System To Manage Complex Commercial Buildings, file e0c31c08-5748-4599-e053-1705fe0aef77
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146
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The hArtes Tool Chain, file e0c31c09-d978-4599-e053-1705fe0aef77
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141
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Looking into the Crystal Ball: From Transistors to the Smart Earth, file e0c31c08-1bb8-4599-e053-1705fe0aef77
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140
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Efficient Hardware Design of Iterative Stencil Loops, file e0c31c11-511f-4599-e053-1705fe0aef77
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135
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EMPhASIS: An EMbedded Public Attention Stress Identification System, file e0c31c0f-da83-4599-e053-1705fe0aef77
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121
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Hw/sw Codesign For Embedded Telecom Systems, file e0c31c10-5560-4599-e053-1705fe0aef77
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109
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EXTRA: Towards an efficient open platform for reconfigurable High Performance Computing, file e0c31c09-6d77-4599-e053-1705fe0aef77
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105
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Partitioning and Mapping for the hArtes European Project, file e0c31c09-238a-4599-e053-1705fe0aef77
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101
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System-level performance estimation strategy for Sw and Hw, file e0c31c11-9752-4599-e053-1705fe0aef77
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99
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A scalable decentralized system for fair token distribution and seamless users onboarding, file e0c31c12-6c8e-4599-e053-1705fe0aef77
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60
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Analog circuits placement: A constraint driven methodology, file e0c31c11-7b3d-4599-e053-1705fe0aef77
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52
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ASSURE: RTL Locking Against an Untrusted Foundry, file e0c31c11-392a-4599-e053-1705fe0aef77
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46
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A Bird’s Eye View on Quantum Computing: Current and Future Trends, file 686086ac-f535-4b4c-b40d-377f278864dc
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42
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Optimizing the Use of Behavioral Locking for High-Level Synthesis, file 6e22b7b8-64cb-4b15-b45c-47d67522f164
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42
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Invited: High-level design methods for hardware security: Is it the right choice?, file 60a29156-b27d-4c6b-ac49-77f75fb2f450
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41
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A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms, file e0c31c0d-2a92-4599-e053-1705fe0aef77
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36
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Automated Fine-Grained CPU Provisioning for Virtual Machines, file e0c31c0d-9adb-4599-e053-1705fe0aef77
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36
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Library functions timing characterization for source-level analysis, file e0c31c11-7b3f-4599-e053-1705fe0aef77
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36
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METHOD FOR LOCATING A DEVICE INSIDE AN AREA, file e0c31c0f-2d67-4599-e053-1705fe0aef77
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35
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A Decentralized Approach to Award Game Achievements, file 243229cd-9459-419e-9640-c65b144d06e6
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29
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ASSURE: RTL Locking Against an Untrusted Foundry, file e0c31c12-e7a1-4599-e053-1705fe0aef77
|
18
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Improving the security and the scalability of the AES algorithm, file e0c31c08-56ce-4599-e053-1705fe0aef77
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17
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On the Design and Characterization of Set Packing Problem on Quantum Annealers, file 305cf765-55ea-4f7c-bd86-278845ef4e2c
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15
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MARC: A resource consumption modeling service for self-aware autonomous agents, file e0c31c0b-c120-4599-e053-1705fe0aef77
|
8
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BuildingRules: A Trigger-Action--Based System to Manage Complex Commercial Buildings, file e0c31c0c-8dc4-4599-e053-1705fe0aef77
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8
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Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization, file ec7d1b29-3819-4cd6-9d55-44cf170f82da
|
8
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hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms, file e0c31c07-e36e-4599-e053-1705fe0aef77
|
5
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On how to accelerate iterative stencil loops: A scalable streaming-based approach, file e0c31c0a-0b83-4599-e053-1705fe0aef77
|
5
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Parallelizing the chambolle algorithm for performance-optimized mapping on FPGA Devices, file e0c31c0a-42d7-4599-e053-1705fe0aef77
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4
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Efficient Hardware Design of Iterative Stencil Loops, file e0c31c0a-46fe-4599-e053-1705fe0aef77
|
4
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|
In Car Audio, file e0c31c07-f97d-4599-e053-1705fe0aef77
|
3
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Automated Fine-Grained CPU Provisioning for Virtual Machines, file e0c31c0a-0b8e-4599-e053-1705fe0aef77
|
3
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|
Plaster: An Embedded FPGA-based Cluster Orchestrator for Accelerated Distributed Algorithms, file e0c31c12-3e21-4599-e053-1705fe0aef77
|
3
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Software and Hardware Techniques for SEU Detection in IP Processors, file e0c31c07-ca4e-4599-e053-1705fe0aef77
|
2
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SPELL: Affecting Thermal Comfort Through Perceptive Techniques, file e0c31c08-2bfc-4599-e053-1705fe0aef77
|
2
|
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A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms, file e0c31c08-57ef-4599-e053-1705fe0aef77
|
2
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Behavioral test generation for the selection of BIST logic, file e0c31c09-e989-4599-e053-1705fe0aef77
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2
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A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops, file e0c31c0a-0a9b-4599-e053-1705fe0aef77
|
2
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The Case for Polymorphic Registers in Dataflow Computing, file e0c31c10-80bf-4599-e053-1705fe0aef77
|
2
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|
MARC: A resource consumption modeling service for self-aware autonomous agents, file e0c31c10-c130-4599-e053-1705fe0aef77
|
2
|
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Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs, file e0c31c07-c1eb-4599-e053-1705fe0aef77
|
1
|
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Dynamic Modeling of Inter-Instruction Effects for Execution Time Estimation, file e0c31c07-c45f-4599-e053-1705fe0aef77
|
1
|
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Functional Test Generation, file e0c31c07-d803-4599-e053-1705fe0aef77
|
1
|
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Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems, file e0c31c07-ea72-4599-e053-1705fe0aef77
|
1
|
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A design methodology to implement memory accesses in High-Level Synthesis, file e0c31c07-f1a4-4599-e053-1705fe0aef77
|
1
|
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The hArtes Tool Chain, file e0c31c07-f97c-4599-e053-1705fe0aef77
|
1
|
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Smart City: tecnologia e creatività a supporto dell’innovazione, file e0c31c08-33e3-4599-e053-1705fe0aef77
|
1
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Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration, file e0c31c08-43ee-4599-e053-1705fe0aef77
|
1
|
|
An open-source, efficient and parameterizable hardware implementation of the AES algorithm, file e0c31c08-5b80-4599-e053-1705fe0aef77
|
1
|
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BlueSentinel: A first approach using iBeacon for an energy efficient occupancy detection system, file e0c31c08-63cd-4599-e053-1705fe0aef77
|
1
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Experimental evaluation and modeling of thermal phenomena on mobile devices, file e0c31c09-4b79-4599-e053-1705fe0aef77
|
1
|
|
PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures, file e0c31c0a-0b8a-4599-e053-1705fe0aef77
|
1
|
|
A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip, file e0c31c0a-1508-4599-e053-1705fe0aef77
|
1
|
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An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs, file e0c31c0a-1acd-4599-e053-1705fe0aef77
|
1
|
|
ReSP: A Non-Intrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration, file e0c31c0a-1c27-4599-e053-1705fe0aef77
|
1
|
|
Combined software and hardware techniques for the design of reliable IP processors, file e0c31c0a-1f98-4599-e053-1705fe0aef77
|
1
|
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A model of soft error effects in generic IP processors, file e0c31c0a-fffc-4599-e053-1705fe0aef77
|
1
|
|
Partitioning of Hw-Sw Embedded Systems: A Metrics-Based Approach, file e0c31c0b-c00c-4599-e053-1705fe0aef77
|
1
|
|
Hw/sw Codesign of Embedded Systems, Int. Conference on Reliable Software Technologies, file e0c31c0c-3891-4599-e053-1705fe0aef77
|
1
|
| Totale |
10.784 |