Since the birth of the Evolvable Hardware (EHW) research field (1993), many FPGA-based evolvable hardware techniques have been devised and proposed to the scientific community. Even if newer EHW systems introduce improvements and new features with respect to the older ones, in most cases they are still based on outdated FPGAs. Thus, they are often limited by the amount of available resources and by the capabilities of the devices used. This paper describes an EHW system based on a Xilinx Virtex-4 FPGA able to exploit features like the direct bitstream manipulation and the two-dimensional dynamic reconfiguration mechanism. Such system has been introduced in 2009 and has been refined in order to cope with real-world applications like the classification problem addressed in this paper.
HERA: Hardware evolution over reconfigurable architectures
BARTOLINI, DAVIDE BASILIO;CARMINATI, MATTEO;SCIUTO, DONATELLA
2011-01-01
Abstract
Since the birth of the Evolvable Hardware (EHW) research field (1993), many FPGA-based evolvable hardware techniques have been devised and proposed to the scientific community. Even if newer EHW systems introduce improvements and new features with respect to the older ones, in most cases they are still based on outdated FPGAs. Thus, they are often limited by the amount of available resources and by the capabilities of the devices used. This paper describes an EHW system based on a Xilinx Virtex-4 FPGA able to exploit features like the direct bitstream manipulation and the two-dimensional dynamic reconfiguration mechanism. Such system has been introduced in 2009 and has been refined in order to cope with real-world applications like the classification problem addressed in this paper.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
