SCIUTO, DONATELLA

SCIUTO, DONATELLA  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Risultati 1 - 20 di 477 (tempo di esecuzione: 0.058 secondi).
Titolo Data di pubblicazione Autori File
A CMOS fault tolerant architecture for switch-level faults 1-gen-1994 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
A Compact Transactional Memory Multiprocessor System on FPGA 1-gen-2010 PALERMO, GIANLUCASCIUTO, DONATELLA +
A comparative evaluation of bit-serial convolvers 1-gen-1989 BREVEGLIERI, LUCA ODDONEDADDA, LUIGISCIUTO, DONATELLA +
A complete test strategy based on interacting and hierarchical FSMs 1-gen-1997 SCIUTO, DONATELLA +
A Data Oriented Approach to the Design of Reconfigurable Stream Decoders 1-gen-2005 AGOSTA, GIOVANNIBRUSCHI, FRANCESCOSANTAMBROGIO, MARCO DOMENICOSCIUTO, DONATELLA
A Design Flow Tailored for Self Dynamic Reconfigurable Architecture 1-gen-2008 CANCARE', FABIOSANTAMBROGIO, MARCO DOMENICOSCIUTO, DONATELLA
A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture 1-gen-2005 FERRANDI, FABRIZIOSANTAMBROGIO, MARCO DOMENICOSCIUTO, DONATELLA
A Design Methodology for the Exploitation of High Level Communication Synthesis 1-gen-2004 BRUSCHI, FRANCESCOSCIUTO, DONATELLA +
A Design Workflow for Dynamically Recongurable Multi-FPGA Systems 1-gen-2010 SANTAMBROGIO, MARCO DOMENICOREDAELLI, FRANCESCOCANCARE', FABIOSCIUTO, DONATELLA +
A fast pipelined complex multiplier: the fault tolerance issue 1-gen-1992 BREVEGLIERI, LUCA ODDONEPIURI, VINCENZOSCIUTO, DONATELLA
A Framework for the Functional Verification of SystemC Models 1-gen-2005 BRUSCHI, FRANCESCOFERRANDI, FABRIZIOSCIUTO, DONATELLA
A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures 1-gen-2006 SANTAMBROGIO, MARCO DOMENICOSCIUTO, DONATELLASPOLETINI, PAOLA +
A hierarchical test generation approach for large controllers 1-gen-2000 SCIUTO, DONATELLA +
A Highly Parallel FPGA-based Evolvable Hardware Architecture 1-gen-2010 CANCARE', FABIOSCIUTO, DONATELLA +
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware 1-gen-2011 RANA, VINCENZOSCIUTO, DONATELLA +
A Light-Weight Network-on-Chip Architecture for Dynamically Recongurable Systems 1-gen-2008 CORBETTA, SIMONERANA, VINCENZOSANTAMBROGIO, MARCO DOMENICOSCIUTO, DONATELLA
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems 1-gen-2003 SAMI, MARIAGIOVANNASCIUTO, DONATELLASILVANO, CRISTINAZACCARIA, VITTORIO +
A Multilevel Testability Assistant For Vlsi Design 1-gen-1992 SCIUTO, DONATELLA +
A new DFT methodology for sequential circuits 1-gen-1995 SCIUTO, DONATELLA +
A new switching-level approach to multiple-output functions synthesis 1-gen-1995 BOLCHINI, CRISTIANASCIUTO, DONATELLA +