The conventional binary weighted array successive approximation register (SAR) analog-to-digital converter (ADC) is the common topology adopted to achieve high efficiency conversion, i.e. with less than 10 fJ/conversion-step, even if it requires extra effort to design and simulate full custom fF or sub-fF capacitors. This paper presents the design and the optimization of an asynchronous SAR ADC with attenuation capacitor achieving an efficiency similar to conventional binary weighted array converters but adopting standard MiM capacitors. A monotonic switching algorithm further reduces the capacitive array consumption while an asynchronous and fully-differential dynamic logic minimizes the digital power consumption. A 10-bit prototype has been fabricated in a standard 0.13-um CMOS technology. At a 0.5-V supply and 200-kSps sampling frequency, the ADC achieves a SNDR of 52.6 dB, an ENOB of 8.45, and a power consumption of 420 nW, corresponding to a figure-of-merit (FOM) of 6 fJ/conversion-step. This efficiency is comparable to the best results published so far and it's the lowest among ADCs in 130-nm or less scaled technology. The ADC core occupies an active area of only 0.045 mm^2.

A 6-fJ/conversion-step 200-kSps Asynchronous SAR ADC with Attenuation Capacitor in 130-nm CMOS adopting Standard MiM Capacitors

BRENNA, STEFANO;BONFANTI, ANDREA GIOVANNI;LACAITA, ANDREA LEONARDO
2014

Abstract

The conventional binary weighted array successive approximation register (SAR) analog-to-digital converter (ADC) is the common topology adopted to achieve high efficiency conversion, i.e. with less than 10 fJ/conversion-step, even if it requires extra effort to design and simulate full custom fF or sub-fF capacitors. This paper presents the design and the optimization of an asynchronous SAR ADC with attenuation capacitor achieving an efficiency similar to conventional binary weighted array converters but adopting standard MiM capacitors. A monotonic switching algorithm further reduces the capacitive array consumption while an asynchronous and fully-differential dynamic logic minimizes the digital power consumption. A 10-bit prototype has been fabricated in a standard 0.13-um CMOS technology. At a 0.5-V supply and 200-kSps sampling frequency, the ADC achieves a SNDR of 52.6 dB, an ENOB of 8.45, and a power consumption of 420 nW, corresponding to a figure-of-merit (FOM) of 6 fJ/conversion-step. This efficiency is comparable to the best results published so far and it's the lowest among ADCs in 130-nm or less scaled technology. The ADC core occupies an active area of only 0.045 mm^2.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/843947
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