This paper presents a low-power high-bit-rate phase modulator based on a digital PLL with single-bit TDC and two-point injection scheme. At high bit rates, this scheme requires a controlled oscillator with wide tuning range and becomes critically sensitive to the delay spread between the two injection paths, considerably degrading the achievable error-vector magnitude and causing significant spectral regrowth. A multi-capacitor-bank oscillator topology with an automatic background regulation of the gains of the banks and a digital adaptive filter for the delay-spread correction are introduced. The phase modulator fabricated in a 65-nm CMOS process synthesizes carriers in the 2.9-to-4.0-GHz range from a 40-MHz crystal reference and it is able to produce a phase change up to +/- 180° with 10-bit resolution in a single reference cycle. Measured EVM at 3.6 GHz is -36 dB for a 10-Mb/s GMSK and a 20-Mb/s QPSK modulation. Power dissipation is 5 mW from a 1.2-V voltage supply, leading to a total energy consumption of 0.25 nJ/bit.

A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power

MARZIN, GIOVANNI;LEVANTINO, SALVATORE;SAMORI, CARLO;LACAITA, ANDREA LEONARDO
2012-01-01

Abstract

This paper presents a low-power high-bit-rate phase modulator based on a digital PLL with single-bit TDC and two-point injection scheme. At high bit rates, this scheme requires a controlled oscillator with wide tuning range and becomes critically sensitive to the delay spread between the two injection paths, considerably degrading the achievable error-vector magnitude and causing significant spectral regrowth. A multi-capacitor-bank oscillator topology with an automatic background regulation of the gains of the banks and a digital adaptive filter for the delay-spread correction are introduced. The phase modulator fabricated in a 65-nm CMOS process synthesizes carriers in the 2.9-to-4.0-GHz range from a 40-MHz crystal reference and it is able to produce a phase change up to +/- 180° with 10-bit resolution in a single reference cycle. Measured EVM at 3.6 GHz is -36 dB for a 10-Mb/s GMSK and a 20-Mb/s QPSK modulation. Power dissipation is 5 mW from a 1.2-V voltage supply, leading to a total energy consumption of 0.25 nJ/bit.
2012
sezele; CMOS; frequency synthesizer; Phase modulation
File in questo prodotto:
File Dimensione Formato  
JSSC_2012.pdf

Accesso riservato

: Post-Print (DRAFT o Author’s Accepted Manuscript-AAM)
Dimensione 3.64 MB
Formato Adobe PDF
3.64 MB Adobe PDF   Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/687047
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 82
  • ???jsp.display-item.citation.isi??? 62
social impact