RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

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Mostrati risultati da 1 a 50 di 189
Titolo Data di pubblicazione Autori File
FSM fault models impact on test performances 1-gen-1993 BOLCHINI, CRISTIANA +
Two-Dimensional Sequential Array Architectures: Design for Testability and Reconfiguration Issues 1-gen-1993 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
A design methodology for the correct specification of VLSI systems 1-gen-1993 BOLCHINI, CRISTIANA +
CMOS Reliability Improvements Through a New Fault Tolerant Technique 1-gen-1994 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
Two-Dimensional Sequential Array Architectures: Design for Testability Approaches 1-gen-1994 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
Design for testability issues in the implementation of sequential array architectures 1-gen-1994 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
A CMOS fault tolerant architecture for switch-level faults 1-gen-1994 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
CASTOR: a computer aided system testability optimizer 1-gen-1994 BOLCHINI, CRISTIANA
CASTOR: an expert advisor for testability enhancement of VLSI systems 1-gen-1994 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
A state encoding for self-checking finite state machines 1-gen-1995 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
Self-checking FSMs based on a constant distance state encoding 1-gen-1995 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
An output/state encoding for self-checking finite state machine 1-gen-1995 BOLCHINI, CRISTIANASCIUTO, DONATELLA
A Wafer Level Testability Approach Based on an Improved Scan Insertion Technique 1-gen-1995 BOLCHINI, CRISTIANAFERRANDI, FABRIZIOSCIUTO, DONATELLA +
A new switching-level approach to multiple-output functions synthesis 1-gen-1995 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
CMOS Fault Tolerant Architectures for Switch level faults 1-gen-1995 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
Innovative design of CMOS fault tolerant structures 1-gen-1995 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
A BDD based algorithm for detecting difficult faults 1-gen-1995 BOLCHINI, CRISTIANASALICE, FABIO +
Towards WSI testable devices: an improved scan insertion technique 1-gen-1995 BOLCHINI, CRISTIANAFERRANDI, FABRIZIOSCIUTO, DONATELLA +
Static redundancy techniques for CMOS gates 1-gen-1996 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
Software methodologies for VHDL code static analysis based on flow graphs 1-gen-1996 BARESI, LUCIANOBOLCHINI, CRISTIANASCIUTO, DONATELLA
Fault detection and fault tolerance issues at CMOS level through AUED encoding 1-gen-1996 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
Redundant faults in TSC networks: definition and removal 1-gen-1996 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Design of Totally Self Checking Checkers for a Class of Constant Hamming Distance Codes 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Software Methodologies for VHDL Code Static Analysis 1-gen-1997 BARESI, LUCIANOBOLCHINI, CRISTIANA
A novel methodology for designing TSC networks based on the parity bit code 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Parity bit code: achieving a complete fault coverage in the design of TSC combinational networks 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
A TSC evaluation function for combinational circuits 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Conditions for the design of circuits with concurrent error detection properties 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
An improved fault tolerant architecture at CMOS level 1-gen-1997 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
Designing networks with error detection properties through the fault-error relation 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
A scalar cost function for analyzing the quality of totally self-checking design methodologies 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Designing ad-hoc codes for the realization of fault tolerant CMOS networks 1-gen-1997 BOLCHINI, CRISTIANASCIUTO, DONATELLA +
Fault analysis in networks with concurrent error detection properties 1-gen-1998 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Fault Analysis for Networks with Concurrent Error Detection Properties 1-gen-1998 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Concurrent error detection at architectural level 1-gen-1998 BOLCHINI, CRISTIANAFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
Guidelines for Property Verification of VHDL Models: an Industrial Perspective 1-gen-1998 ALLARA, ALBERTOBOLCHINI, CRISTIANACOMAI, SARASCIUTO, DONATELLA +
High Level Synthesis for Concurrent Error Detection 1-gen-1998 BOLCHINI, CRISTIANAFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
A synthesis methodology aimed at improving the quality of TSC devices 1-gen-1999 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
The design of Self-Checking Systems 1-gen-2000 BOLCHINI, CRISTIANASALICE, FABIO
Design of VHDL based Totally Self-Checking Finite State machine and Data Path descriptions 1-gen-2000 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
Designing Reliable Embedded Systems Based on 32 Bit Microprocessors 1-gen-2001 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Reliability Properties Assessment at System Level: A Co-design Framework 1-gen-2001 BOLCHINI, CRISTIANAPOMANTE, LUIGISALICE, FABIOSCIUTO, DONATELLA
On-Line Fault Detection in a Hardware/Software Co-design Environment 1-gen-2001 BOLCHINI, CRISTIANAPOMANTE, LUIGISALICE, FABIOSCIUTO, DONATELLA
A Software Methodology for detecting Hardware Faults in VLIW Data Paths 1-gen-2001 BOLCHINI, CRISTIANAPOMANTE, LUIGISALICE, FABIO
Physical and Logical Data Structures for Very Small Databases 1-gen-2002 BOLCHINI, CRISTIANASALICE, FABIOSCHREIBER, FABIO ALBERTOTANCA, LETIZIA
Smart Card Embedded Information Systems: a Methodology for Privacy Oriented Architectural Design 1-gen-2002 BOLCHINI, CRISTIANASCHREIBER, FABIO ALBERTO
Designing Self-Checking FPGAs Through Error Detection Codes 1-gen-2002 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems 1-gen-2002 BOLCHINI, CRISTIANAPOMANTE, LUIGISALICE, FABIOSCIUTO, DONATELLA
Reliability Properties Assessment at System Level: A Co-design Framework 1-gen-2002 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
Logical and Physical Design Issues for Smart Card Databases 1-gen-2003 BOLCHINI, CRISTIANASALICE, FABIOSCHREIBER, FABIO ALBERTOTANCA, LETIZIA
Mostrati risultati da 1 a 50 di 189
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