CMOS Reliability Improvements Through a New Fault Tolerant Technique

A CMOS gate structure tolerating all single transistor stuck-at (TSA) faults and a large set of multiple faults is presented. Such structure is based on the simultaneous implementation of both the natural and complemented form of the deisred output; such implementation is easily modifiable to achieve fault tolerance and to obtain detectability of most of the faults which are not tolerated since they cause the two output lines to share the same value. Usually, production of the natural and complemente form of the output signal does not require to double the number of transistors, thus resulting cheaper (in terms of area) than other approaches.