Testing of array architectures is an important issue because of the relevance that these structures are assuming in VLSI/WSI designs. The DfT techniques presented in this paper represent a possible approach to allow the verification of the cells composing the entire structure. The structural methodologies cope with the accessibility problems by modifying the interconnection network to “isolate” the cell in exam from the others; the functional approach modifies the cell making it transparent with respect to the data flow if the cell is not being tested. Both techniques aim at defining a sequential array architecture whose elements can be tested by applying patterns defined for the single cell and achieving the same coverage notwithstanding the embedding constituted by the array interconnections.

Two-Dimensional Sequential Array Architectures: Design for Testability Approaches

BOLCHINI, CRISTIANA;SCIUTO, DONATELLA
1994-01-01

Abstract

Testing of array architectures is an important issue because of the relevance that these structures are assuming in VLSI/WSI designs. The DfT techniques presented in this paper represent a possible approach to allow the verification of the cells composing the entire structure. The structural methodologies cope with the accessibility problems by modifying the interconnection network to “isolate” the cell in exam from the others; the functional approach modifies the cell making it transparent with respect to the data flow if the cell is not being tested. Both techniques aim at defining a sequential array architecture whose elements can be tested by applying patterns defined for the single cell and achieving the same coverage notwithstanding the embedding constituted by the array interconnections.
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems
078031915X
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/666929
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