The paper proposes an approach for designing TSC networks by means of error detecting code application, based on the analysis of the desired fault-error relation. The network structure is analyzed by taking into account each possible fault, belonging to the adopted fault set, and by verifying if the produced error is detectable with respect to the adopted encoding. If undetectable faults are located the network is locally modified, so that area overheads for TSC designs are limited.

Designing networks with error detection properties through the fault-error relation

BOLCHINI, CRISTIANA;SALICE, FABIO;SCIUTO, DONATELLA
1997-01-01

Abstract

The paper proposes an approach for designing TSC networks by means of error detecting code application, based on the analysis of the desired fault-error relation. The network structure is analyzed by taking into account each possible fault, belonging to the adopted fault set, and by verifying if the produced error is detectable with respect to the adopted encoding. If undetectable faults are located the network is locally modified, so that area overheads for TSC designs are limited.
1997
Proc. IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems
0818681683
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/654965
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