Different redundancy techniques are evaluated with respect to transistor stuck-at fault tolerance. In particular, transistor stuck open and stuck-on faults are considered. First the results achieved by the quadruplicating technique are examined by applying it to combinational CMOS gates both at the net level and at the transistor level. The triple modular redundancy approach is then analyzed at the CMOS gate level and compared with the quadruplicating technique. The traditional static CMOS structure is adopted as a reference model for reliability comparisons.

Static redundancy techniques for CMOS gates

BOLCHINI, CRISTIANA;SCIUTO, DONATELLA;
1996-01-01

Abstract

Different redundancy techniques are evaluated with respect to transistor stuck-at fault tolerance. In particular, transistor stuck open and stuck-on faults are considered. First the results achieved by the quadruplicating technique are examined by applying it to combinational CMOS gates both at the net level and at the transistor level. The triple modular redundancy approach is then analyzed at the CMOS gate level and compared with the quadruplicating technique. The traditional static CMOS structure is adopted as a reference model for reliability comparisons.
Proc. IEEE Int. Symposium on Circuits and Systems. Circuits and Systems Connecting the World
0780330730
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/654957
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