Software Methodologies for VHDL Code Static Analysis

At a high level of abstraction, the VHDL specification of the functionalities that a circuit can perform is given by defining the behavioral model. Similarity with procedural programming languages is suggested to tailor some software analysis techniques to VHDL behavioral description analysis. The aim is to retrieve information on the final circuit from its specifications. This paper presents several analyses of the code aimed at identifying significant properties of the final circuit from the synthesis and testability points of view.