RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

SILVANO, CRISTINA
 Distribuzione geografica
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Continente #
NA - Nord America 12.144
EU - Europa 3.876
AS - Asia 1.256
OC - Oceania 30
AF - Africa 23
SA - Sud America 9
Continente sconosciuto - Info sul continente non disponibili 6
Totale 17.344
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Nazione #
US - Stati Uniti d'America 11.978
IT - Italia 1.417
UA - Ucraina 481
SE - Svezia 431
VN - Vietnam 388
DE - Germania 330
SG - Singapore 314
FI - Finlandia 257
CN - Cina 227
GB - Regno Unito 215
AT - Austria 201
CA - Canada 164
ES - Italia 154
IE - Irlanda 144
IN - India 140
NL - Olanda 81
FR - Francia 45
BE - Belgio 39
TH - Thailandia 34
AU - Australia 27
ID - Indonesia 25
JO - Giordania 24
JP - Giappone 23
KR - Corea 20
CH - Svizzera 19
HK - Hong Kong 17
GR - Grecia 14
MY - Malesia 12
RU - Federazione Russa 9
CI - Costa d'Avorio 7
TR - Turchia 7
AL - Albania 6
BJ - Benin 6
BR - Brasile 6
CZ - Repubblica Ceca 6
EU - Europa 6
MU - Mauritius 6
PK - Pakistan 5
PT - Portogallo 5
TW - Taiwan 5
IR - Iran 4
PL - Polonia 4
RO - Romania 4
HR - Croazia 3
LV - Lettonia 3
NO - Norvegia 3
NZ - Nuova Zelanda 3
ZA - Sudafrica 3
AE - Emirati Arabi Uniti 2
AR - Argentina 2
AZ - Azerbaigian 2
PH - Filippine 2
SA - Arabia Saudita 2
BO - Bolivia 1
DK - Danimarca 1
DO - Repubblica Dominicana 1
DZ - Algeria 1
EE - Estonia 1
HU - Ungheria 1
IL - Israele 1
LK - Sri Lanka 1
LT - Lituania 1
OM - Oman 1
PA - Panama 1
RS - Serbia 1
Totale 17.344
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Città #
Fairfield 2.057
Woodbridge 1.378
Ashburn 1.008
Houston 1.004
Seattle 905
Wilmington 811
Cambridge 753
Chandler 679
Ann Arbor 626
Jacksonville 288
Milan 284
Santa Clara 271
Boardman 264
Dearborn 245
Singapore 211
Dong Ket 204
Vienna 200
Lawrence 187
Medford 173
Ottawa 152
Málaga 149
Dublin 141
San Diego 96
Helsinki 91
Beijing 74
Verona 73
Des Moines 67
Norwalk 42
Brussels 34
Amsterdam 33
New Delhi 33
Rome 33
Bangkok 31
Redwood City 30
Shanghai 29
London 27
Amman 24
Jakarta 23
Auburn Hills 22
Frankfurt am Main 22
New York 22
Delhi 21
Mountain View 21
Los Angeles 20
Indiana 19
Miami 19
Mumbai 19
Princeton 19
Naples 18
Falls Church 16
Padova 16
Brescia 15
Tokyo 15
Redmond 14
Bologna 13
Trieste 13
Collegno 12
Kuala Lumpur 12
Nanjing 11
Sydney 11
Brisbane 10
Phoenix 10
Seongnam 10
Kunming 9
Turin 9
's-Hertogenbosch 8
Bergamo 8
Florence 8
Hong Kong 8
San Donato Milanese 8
Abidjan 7
Catania 7
Columbus 7
Groningen 7
Hefei 7
Washington 7
Alessandria 6
Carnate 6
Cotonou 6
Grugliasco 6
Guangzhou 6
Kilburn 6
Livorno 6
Nanchang 6
Paris 6
Trento 6
Yellow Springs 6
Berlin 5
Dallas 5
Illasi 5
Jinan 5
Kolkata 5
Lecco 5
Lugano 5
Parma 5
Zurich 5
Atlanta 4
Austin 4
Bern 4
Chiswick 4
Totale 13.357
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Nome #
Progettazione digitale 756
Accelerating Binary and Mixed-Precision NNs Inference on STMicroelectronics Embedded NPU with Digital In-Memory-Computing 393
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level 196
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis 165
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors 163
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 152
Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering 146
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures. 145
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods 141
Efficiency and Scalability of Barrier Synchronization on NoC Based Many-core Architectures 140
Throughput balancing for energy efficient near-threshold manycores 137
Accelerating a Geometric Approach to Molecular Docking with OpenACC 137
Low-power Architectures for Mobile Systems 136
Branch Prediction Techniques for Low-Power VLIW Processors 136
A Data Protection Unit for NoC-based Architectures 136
The ANTAREX approach to autotuning and adaptivity for energy efficient HPC Systems 136
A System-Level Methodology for Fast Multi-Objective Design Space Exploration 135
Design Space Exploration Supporting Run-time Resource Management 133
Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures 132
A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems 130
DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling 128
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures 127
A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip 126
An Efficient Synchronization Technique for Multiprocessor Systems on-Chip 124
Application autotuning to support runtime adaptivity in multicore architectures 124
mARGOt: a Dynamic Autotuning Framework for Self-aware Approximate Computing 123
Mapping and Topology Customization Approaches for Application-Specific STNoC Designs 120
SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications 119
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration 119
A Security Monitoring Service for NoCs 117
MiCOMP: Mitigating the Compiler Phase-Ordering Problem Using Optimization Sub-Sequences and Machine Learning 116
An instruction-level methodology for power estimation and optimization of embedded VLIW cores 115
A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip 115
A Design Framework to Efficiently Explore Energy-Delay Tradeoffs 114
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors 114
A Topology Design Customization Approach for STNoC 114
A Power-Efficient Methodology for Mapping Applications on Multi-Processor System-on-Chip Architectures 114
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models 113
ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems 110
Construction Techniques for Systematic SEC-DED Codes with Single Byte Error Detection and Partial Correction Capability for Computer Memory Systems 110
Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics 109
Exploiting TLM and Object Introspection for System-Level Simulation 109
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip 109
Parallel paradigms and run-time management techniques for many-core architectures: 2parma approach 108
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach 106
A survey on compiler autotuning using machine learning 106
Robust Optimization of SoC Architectures: A Multi-Scenario Approach 106
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 104
COBAYN: Compiler autotuning framework using Bayesian networks 104
OpenCL application auto-tuning and run-time resource management for multi-core platforms 104
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 103
State encoding for low power embedded controllers 103
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems 102
Floorplan-aware hierarchical NoC topology with GALS interfaces 102
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 102
Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips 102
ANTAREX - AutoTuning and adaptivity approach for energy efficient eXascale HPC systems 102
Decision-theoretic Exploration of Multi-Processor Platforms 100
An Instruction-Level Energy Model for Embedded VLIW Architectures 100
A framework for Compiler Level statistical analysis over customized VLIW architecture 100
A system-level exploration of power delivery architectures for near-threshold manycores considering performance constraints 99
An Efficient Monte Carlo-based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System 99
Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming 98
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture 98
Combining application adaptivity and system-wide Resource Management on multi-core platforms 98
Predictive modeling methodology for compiler phase-ordering 97
A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization 97
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach 95
Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints 95
The ANTAREX domain specific language for high performance computing 94
Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques 93
Efficient Architecture/Compiler Co-Exploration Using Analytical Models 93
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems 93
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures 93
A Monitoring System for NoCs 92
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems 92
Power Exploration for Embedded VLIW Architectures 92
Parallel paradigms and run-time management techniques for many-core architectures 92
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications 92
PIRATE: A Framework for Power/Performance Exploration of Network-On-Chip Architectures 92
Instruction-Level Power Estimation for Embedded VLIW Cores 91
Multi-Objective Co-Exploration of Source Code Transformations and Design Space Architecture for Low-Power Embedded Systems 91
Low-Power Data Forwarding for VLIW Embedded Architectures 91
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors 91
A Bayesian network approach for compiler auto-tuning for embedded processors 91
Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs 91
Exploiting OpenMP and OpenACC to accelerate a geometric approach to molecular docking in heterogeneous HPC nodes 91
Power Optimization of System-Level Address Buses based on Software Profiling 91
An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures 90
The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems 90
Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems 89
Design Space Exploration for Orlando Ultra Low-Power Convolutional Neural Network SoC 89
Architecture Optimization of Application-Specific Implicit Instructions 88
Variability-Aware Voltage Island Management for Near-Threshold Computing with Performance Guarantees 88
A conceptual analysis framework for low power design of embedded systems 87
Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations 84
Application-Specific Topology Design Customization for STNoC 84
OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces 84
Automatic Generation of Error Control Codes for Computer Applications 83
Secure Memory Accesses on Networks-on-Chip 83
Totale 11.849
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Categoria #
all - tutte 53.930
article - articoli 11.708
book - libri 1.836
conference - conferenze 33.782
curatela - curatele 1.640
other - altro 0
patent - brevetti 1.386
selected - selezionate 0
volume - volumi 3.578
Totale 107.860
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20203.048 0 0 0 0 0 650 600 456 582 215 407 138
2020/20212.689 216 150 265 143 195 126 198 243 153 359 171 470
2021/20221.784 77 224 158 125 231 109 91 102 86 102 176 303
2022/20231.949 240 102 49 253 185 243 20 121 281 209 132 114
2023/20241.348 102 209 72 192 95 154 63 123 22 109 54 153
2024/20251.066 54 79 128 115 492 198 0 0 0 0 0 0
Totale 17.536