SILVANO, CRISTINA
 Distribuzione geografica
Continente #
NA - Nord America 10736
EU - Europa 2670
AS - Asia 587
AF - Africa 6
Continente sconosciuto - Info sul continente non disponibili 6
SA - Sud America 3
OC - Oceania 2
Totale 14010
Nazione #
US - Stati Uniti d'America 10582
IT - Italia 850
UA - Ucraina 470
SE - Svezia 420
VN - Vietnam 382
DE - Germania 252
AT - Austria 201
FI - Finlandia 165
GB - Regno Unito 158
CA - Canada 154
CN - Cina 133
IN - India 48
BE - Belgio 41
NL - Olanda 35
FR - Francia 31
KR - Corea 13
GR - Grecia 12
AL - Albania 6
EU - Europa 6
MU - Mauritius 6
ES - Italia 5
PT - Portogallo 5
RU - Federazione Russa 5
CH - Svizzera 4
PK - Pakistan 4
RO - Romania 4
BR - Brasile 3
TR - Turchia 3
AU - Australia 2
CZ - Repubblica Ceca 2
JP - Giappone 2
DK - Danimarca 1
HU - Ungheria 1
ID - Indonesia 1
NO - Norvegia 1
RS - Serbia 1
TW - Taiwan 1
Totale 14010
Città #
Fairfield 2042
Woodbridge 1377
Houston 997
Seattle 900
Ashburn 857
Wilmington 808
Cambridge 740
Chandler 631
Ann Arbor 625
Jacksonville 285
Dearborn 237
Dong Ket 202
Vienna 201
Lawrence 186
Medford 172
Milan 163
Ottawa 151
San Diego 95
Beijing 70
Des Moines 67
Boardman 56
Verona 50
Norwalk 42
Brussels 36
Redwood City 30
Amsterdam 25
Auburn Hills 22
Rome 22
Mountain View 21
Indiana 19
Princeton 19
Falls Church 16
Redmond 14
Los Angeles 10
Nanjing 10
Seongnam 10
Phoenix 9
Kunming 8
London 8
San Donato Milanese 8
Hefei 7
Bergamo 6
Brescia 6
Groningen 6
Grugliasco 6
Nanchang 6
New York 6
Yellow Springs 6
Dallas 5
Jinan 5
Livorno 5
Padova 5
Gavirate 4
Athens 3
Atlanta 3
Bologna 3
Bolzano 3
Castiglione Delle Stiviere 3
Duncan 3
Erbusco 3
Guangzhou 3
Helsinki 3
Hillsboro 3
Horia 3
Izmir 3
Kaisheim 3
Munich 3
Olgiate Molgora 3
Parma 3
Pozzuoli 3
San Francisco 3
Seregno 3
Trento 3
Adrano 2
Alexandria 2
Bangalore 2
Barcelona 2
Baselga di Pinè 2
Berlin 2
Cantu 2
Catania 2
Changsha 2
College Park 2
Como 2
Enterprise 2
Fidenza 2
Fiorenzuola d'Arda 2
Foggia 2
Grafing 2
Greenbelt 2
Hangzhou 2
Lendinara 2
Mestre 2
Mirasole 2
Naples 2
Obolon 2
Olching 2
Pontassieve 2
Ragusa 2
Reggio Nell'emilia 2
Totale 11428
Nome #
Progettazione digitale 309
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level 172
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis 144
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 142
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors 141
Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering 137
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods 128
Branch Prediction Techniques for Low-Power VLIW Processors 127
A System-Level Methodology for Fast Multi-Objective Design Space Exploration 125
Efficiency and Scalability of Barrier Synchronization on NoC Based Many-core Architectures 122
Throughput balancing for energy efficient near-threshold manycores 122
Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures 121
The ANTAREX approach to autotuning and adaptivity for energy efficient HPC Systems 120
Design Space Exploration Supporting Run-time Resource Management 120
A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems 119
Accelerating a Geometric Approach to Molecular Docking with OpenACC 119
A Data Protection Unit for NoC-based Architectures 118
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures. 118
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures 118
Mapping and Topology Customization Approaches for Application-Specific STNoC Designs 115
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration 115
Low-power Architectures for Mobile Systems 112
Application autotuning to support runtime adaptivity in multicore architectures 111
An instruction-level methodology for power estimation and optimization of embedded VLIW cores 107
A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip 107
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors 106
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models 105
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip 104
SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications 104
An Efficient Synchronization Technique for Multiprocessor Systems on-Chip 102
A Security Monitoring Service for NoCs 102
mARGOt: a Dynamic Autotuning Framework for Self-aware Approximate Computing 102
A Power-Efficient Methodology for Mapping Applications on Multi-Processor System-on-Chip Architectures 102
DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling 101
ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems 100
A Topology Design Customization Approach for STNoC 99
State encoding for low power embedded controllers 99
Construction Techniques for Systematic SEC-DED Codes with Single Byte Error Detection and Partial Correction Capability for Computer Memory Systems 99
Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics 98
A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip 98
Floorplan-aware hierarchical NoC topology with GALS interfaces 98
Robust Optimization of SoC Architectures: A Multi-Scenario Approach 97
Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips 97
Exploiting TLM and Object Introspection for System-Level Simulation 93
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture 93
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach 91
COBAYN: Compiler autotuning framework using Bayesian networks 91
A system-level exploration of power delivery architectures for near-threshold manycores considering performance constraints 90
Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques 89
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 89
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems 89
MiCOMP: Mitigating the Compiler Phase-Ordering Problem Using Optimization Sub-Sequences and Machine Learning 89
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems 88
Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming 88
PIRATE: A Framework for Power/Performance Exploration of Network-On-Chip Architectures 88
A survey on compiler autotuning using machine learning 88
Decision-theoretic Exploration of Multi-Processor Platforms 87
Efficient Architecture/Compiler Co-Exploration Using Analytical Models 87
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors 86
Parallel paradigms and run-time management techniques for many-core architectures: 2parma approach 86
Power Optimization of System-Level Address Buses based on Software Profiling 86
ANTAREX - AutoTuning and adaptivity approach for energy efficient eXascale HPC systems 85
An Instruction-Level Energy Model for Embedded VLIW Architectures 84
Power Exploration for Embedded VLIW Architectures 84
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach 84
OpenCL application auto-tuning and run-time resource management for multi-core platforms 84
Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints 84
Predictive modeling methodology for compiler phase-ordering 83
Low-Power Data Forwarding for VLIW Embedded Architectures 82
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 81
A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization 81
Instruction-Level Power Estimation for Embedded VLIW Cores 80
Multi-Objective Co-Exploration of Source Code Transformations and Design Space Architecture for Low-Power Embedded Systems 80
Secure Memory Accesses on Networks-on-Chip 80
Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems 79
Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations 79
A framework for Compiler Level statistical analysis over customized VLIW architecture 79
Parallel paradigms and run-time management techniques for many-core architectures 79
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications 79
An Efficient Monte Carlo-based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System 79
Combining application adaptivity and system-wide Resource Management on multi-core platforms 79
Multi-Accuracy Power and Performance Transaction-Level Modeling 78
Variability-Aware Voltage Island Management for Near-Threshold Computing with Performance Guarantees 78
Automatic Generation of Error Control Codes for Computer Applications 76
A Monitoring System for NoCs 76
OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces 76
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures 76
Design Space Exploration for Orlando Ultra Low-Power Convolutional Neural Network SoC 75
Thermal-Aware Datapath Merging for Coarse-Grained Reconfigurable Processors 74
Significant papers from the first 25 years of the FPL conference 74
Application-Specific Topology Design Customization for STNoC 73
An industrial design space exploration framework for supporting run-time resource management on multi-core systems 73
A Bayesian network approach for compiler auto-tuning for embedded processors 73
Systematic AUED codes for self-checking architectures 73
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems 72
An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures 72
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 71
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction 71
Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs 71
Exploiting OpenMP and OpenACC to accelerate a geometric approach to molecular docking in heterogeneous HPC nodes 71
Totale 9728
Categoria #
all - tutte 21011
article - articoli 4529
book - libri 673
conference - conferenze 13378
curatela - curatele 513
other - altro 0
patent - brevetti 462
selected - selezionate 0
volume - volumi 1456
Totale 42022


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2017/20181086 0000 00 264467 636619036
2018/20192132 19133911 5382 6018 50386746655
2019/20204663 31127592363 594646 594454 578214405137
2020/20212670 215149264143 194123 197242 151357169466
2021/20221771 76224156124 229108 91101 86101174301
2022/20231097 23910249253 183241 300 0000
Totale 14186