RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

SILVANO, CRISTINA
 Distribuzione geografica
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Continente #
NA - Nord America 11.593
EU - Europa 3.572
AS - Asia 770
OC - Oceania 29
AF - Africa 16
Continente sconosciuto - Info sul continente non disponibili 6
SA - Sud America 6
Totale 15.992
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Nazione #
US - Stati Uniti d'America 11.429
IT - Italia 1.237
UA - Ucraina 478
SE - Svezia 429
VN - Vietnam 386
DE - Germania 305
FI - Finlandia 242
GB - Regno Unito 205
AT - Austria 199
CN - Cina 181
CA - Canada 164
ES - Italia 154
IE - Irlanda 144
IN - India 87
FR - Francia 43
NL - Olanda 42
BE - Belgio 37
AU - Australia 26
SG - Singapore 25
JO - Giordania 24
KR - Corea 20
GR - Grecia 14
JP - Giappone 13
CH - Svizzera 10
HK - Hong Kong 9
CI - Costa d'Avorio 7
AL - Albania 6
EU - Europa 6
MU - Mauritius 6
RU - Federazione Russa 6
TR - Turchia 6
BR - Brasile 5
CZ - Repubblica Ceca 5
PT - Portogallo 5
PK - Pakistan 4
RO - Romania 4
HR - Croazia 3
ID - Indonesia 3
NZ - Nuova Zelanda 3
TW - Taiwan 3
AE - Emirati Arabi Uniti 2
IR - Iran 2
SA - Arabia Saudita 2
TH - Thailandia 2
ZA - Sudafrica 2
BO - Bolivia 1
DK - Danimarca 1
DZ - Algeria 1
HU - Ungheria 1
NO - Norvegia 1
OM - Oman 1
RS - Serbia 1
Totale 15.992
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Città #
Fairfield 2.057
Woodbridge 1.378
Houston 1.004
Ashburn 995
Seattle 905
Wilmington 811
Cambridge 751
Chandler 679
Ann Arbor 626
Jacksonville 288
Milan 246
Dearborn 245
Dong Ket 204
Vienna 199
Lawrence 187
Medford 173
Ottawa 152
Málaga 149
Dublin 141
San Diego 96
Helsinki 79
Beijing 74
Des Moines 67
Verona 66
Boardman 57
Norwalk 42
Brussels 32
Redwood City 30
Rome 27
Amsterdam 26
Shanghai 25
Amman 24
Auburn Hills 22
London 21
Mountain View 21
Indiana 19
Miami 19
Princeton 19
Naples 18
New York 17
Falls Church 16
Redmond 14
Collegno 12
Delhi 12
Trieste 12
Los Angeles 11
Sydney 11
Brescia 10
Brisbane 10
Nanjing 10
Padova 10
Phoenix 10
Seongnam 10
Frankfurt am Main 9
Mumbai 9
Tokyo 9
Bergamo 8
Bologna 8
Kunming 8
San Donato Milanese 8
Abidjan 7
Columbus 7
Hefei 7
Singapore 7
Alessandria 6
Carnate 6
Groningen 6
Grugliasco 6
Kilburn 6
Livorno 6
Nanchang 6
Trento 6
Yellow Springs 6
Catania 5
Dallas 5
Florence 5
Hong Kong 5
Illasi 5
Jinan 5
Kolkata 5
Lecco 5
Paris 5
Parma 5
Turin 5
Atlanta 4
Bern 4
Chiswick 4
Gavirate 4
Ghaziabad 4
Guangzhou 4
New Delhi 4
Venice 4
Agnadello 3
Athens 3
Bolzano 3
Castiglione Delle Stiviere 3
Cortenuova 3
Dalmine 3
Duncan 3
Enna 3
Totale 12.391
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Nome #
Progettazione digitale 614
Accelerating Binary and Mixed-Precision NNs Inference on STMicroelectronics Embedded NPU with Digital In-Memory-Computing 204
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level 188
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis 158
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors 154
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 147
Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering 139
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures. 136
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods 135
Efficiency and Scalability of Barrier Synchronization on NoC Based Many-core Architectures 133
A System-Level Methodology for Fast Multi-Objective Design Space Exploration 132
Throughput balancing for energy efficient near-threshold manycores 132
A Data Protection Unit for NoC-based Architectures 131
Branch Prediction Techniques for Low-Power VLIW Processors 130
Accelerating a Geometric Approach to Molecular Docking with OpenACC 130
The ANTAREX approach to autotuning and adaptivity for energy efficient HPC Systems 129
Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures 128
Design Space Exploration Supporting Run-time Resource Management 127
Low-power Architectures for Mobile Systems 126
A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems 125
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures 123
DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling 121
A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip 120
Application autotuning to support runtime adaptivity in multicore architectures 119
Mapping and Topology Customization Approaches for Application-Specific STNoC Designs 117
An Efficient Synchronization Technique for Multiprocessor Systems on-Chip 116
mARGOt: a Dynamic Autotuning Framework for Self-aware Approximate Computing 116
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration 116
A Security Monitoring Service for NoCs 115
SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications 112
An instruction-level methodology for power estimation and optimization of embedded VLIW cores 111
A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip 111
A Power-Efficient Methodology for Mapping Applications on Multi-Processor System-on-Chip Architectures 111
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models 111
A Topology Design Customization Approach for STNoC 109
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors 108
Construction Techniques for Systematic SEC-DED Codes with Single Byte Error Detection and Partial Correction Capability for Computer Memory Systems 107
Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics 106
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip 106
A Design Framework to Efficiently Explore Energy-Delay Tradeoffs 105
ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems 103
Robust Optimization of SoC Architectures: A Multi-Scenario Approach 103
Exploiting TLM and Object Introspection for System-Level Simulation 102
MiCOMP: Mitigating the Compiler Phase-Ordering Problem Using Optimization Sub-Sequences and Machine Learning 102
State encoding for low power embedded controllers 101
Floorplan-aware hierarchical NoC topology with GALS interfaces 101
Parallel paradigms and run-time management techniques for many-core architectures: 2parma approach 100
A survey on compiler autotuning using machine learning 100
Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips 99
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 98
A system-level exploration of power delivery architectures for near-threshold manycores considering performance constraints 97
COBAYN: Compiler autotuning framework using Bayesian networks 97
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach 97
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems 96
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 95
ANTAREX - AutoTuning and adaptivity approach for energy efficient eXascale HPC systems 95
An Instruction-Level Energy Model for Embedded VLIW Architectures 94
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture 94
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 93
Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming 93
An Efficient Monte Carlo-based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System 93
OpenCL application auto-tuning and run-time resource management for multi-core platforms 93
Decision-theoretic Exploration of Multi-Processor Platforms 92
A framework for Compiler Level statistical analysis over customized VLIW architecture 92
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach 91
Predictive modeling methodology for compiler phase-ordering 91
A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization 91
Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques 90
Efficient Architecture/Compiler Co-Exploration Using Analytical Models 90
A Monitoring System for NoCs 90
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems 90
PIRATE: A Framework for Power/Performance Exploration of Network-On-Chip Architectures 90
Power Optimization of System-Level Address Buses based on Software Profiling 90
Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints 90
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors 89
Combining application adaptivity and system-wide Resource Management on multi-core platforms 89
Multi-Objective Co-Exploration of Source Code Transformations and Design Space Architecture for Low-Power Embedded Systems 88
Power Exploration for Embedded VLIW Architectures 88
A Bayesian network approach for compiler auto-tuning for embedded processors 87
The ANTAREX domain specific language for high performance computing 87
Exploiting OpenMP and OpenACC to accelerate a geometric approach to molecular docking in heterogeneous HPC nodes 86
Instruction-Level Power Estimation for Embedded VLIW Cores 85
Low-Power Data Forwarding for VLIW Embedded Architectures 85
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems 85
Design Space Exploration for Orlando Ultra Low-Power Convolutional Neural Network SoC 85
Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems 84
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications 84
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures 84
Variability-Aware Voltage Island Management for Near-Threshold Computing with Performance Guarantees 84
An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures 83
Parallel paradigms and run-time management techniques for many-core architectures 83
Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs 82
Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations 81
Application-Specific Topology Design Customization for STNoC 81
Automatic Generation of Error Control Codes for Computer Applications 81
Secure Memory Accesses on Networks-on-Chip 81
OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces 81
Architecture Optimization of Application-Specific Implicit Instructions 81
Significant papers from the first 25 years of the FPL conference 81
Dynamic Configuration of Application-Specific Implicit Instructions for Embedded Pipelined Processors 80
Totale 10.976
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Categoria #
all - tutte 43.109
article - articoli 9.509
book - libri 1.422
conference - conferenze 27.099
curatela - curatele 1.176
other - altro 0
patent - brevetti 997
selected - selezionate 0
volume - volumi 2.906
Totale 86.218
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/20191.797 0 0 0 0 0 0 0 0 0 388 751 658
2019/20204.693 311 277 92 367 598 650 600 456 582 215 407 138
2020/20212.689 216 150 265 143 195 126 198 243 153 359 171 470
2021/20221.784 77 224 158 125 231 109 91 102 86 102 176 303
2022/20231.949 240 102 49 253 185 243 20 121 281 209 132 114
2023/20241.059 102 209 72 192 95 154 63 123 22 27 0 0
Totale 16.181