Recently, manycore architectures are widely adopted for providing the increasing throughput demands and requirements imposed by software complexity and volume explosion. At the same time, the threat of Dark Silicon points to the direction of energy efficient platforms. Near Threshold Computing (NTC) paradigm has recently emerged as the premise of energy efficient operation at the expense of performance degradation, which can be compensated through massive parallelization. In this paper, we propose a runtime management scheme for improved NTC many core energy efficiency. Assuming a feasible, low overhead Power Delivery Network (PDN) for NTC, we propose an algorithm for balancing throughput under process (and workload) variability that sustains performance while reducing power 43.5% on average. Through an extensive experimental campaign, we show the efficiency of the proposed approach for configuring NTC many core architectures.

Throughput balancing for energy efficient near-threshold manycores

STAMELAKOS, IOANNIS;PALERMO, GIANLUCA;SILVANO, CRISTINA
2016-01-01

Abstract

Recently, manycore architectures are widely adopted for providing the increasing throughput demands and requirements imposed by software complexity and volume explosion. At the same time, the threat of Dark Silicon points to the direction of energy efficient platforms. Near Threshold Computing (NTC) paradigm has recently emerged as the premise of energy efficient operation at the expense of performance degradation, which can be compensated through massive parallelization. In this paper, we propose a runtime management scheme for improved NTC many core energy efficiency. Assuming a feasible, low overhead Power Delivery Network (PDN) for NTC, we propose an algorithm for balancing throughput under process (and workload) variability that sustains performance while reducing power 43.5% on average. Through an extensive experimental campaign, we show the efficiency of the proposed approach for configuring NTC many core architectures.
Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016
9781509007332
Energy Efficiency; Low Power Design; Manycore Architectures; Near-Threshold Computing; Modeling and Simulation; Hardware and Architecture; Control and Optimization
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1026256
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