PIRATE: A Framework for Power/Performance Exploration of Network-On-Chip Architectures

In this paper, we address the problem of high-level exploration of Network-on-Chip (NoC) architectures to early evaluate power/performance trade-offs. The main goal of this work is to propose a methodology supported by a design framework (namely, PIRATE) to generate and to simulate a configurable NoC–IP core for the power/performance exploration of the on-chip interconnection network. The NoC–IP core is composed of a set of parameterized modules, such as interconnection elements and switches, to form different on-chip micronetwork topologies. The proposed framework has been applied to explore several network topologies by varying the workload and to analyze a case study designed for cryptographic hardware acceleration in high performance web server systems.