This paper describes a technique for modeling and estimating the power consumptionat the system-level for embedded VLIW (Very Long Instruction Word) architectures. The method is based on a hierarchy of dynamic power estimation engines: from the instruction-level down to the gate/transistor-level. Power macro-models have been developed for the main components of the system: theVLIW core, the register file, the instruction and data caches. The main goals to define a system-level simulation framework for the dynamic profiling of the power behavior during the software execution, providing also a break-down of the power contributions due to the single components of the system. The proposed approach has been applied to the Lx family of scalable embedded VLIWprocessors, jointly designed by STMicroelectronics and HPLabs. Experimental results, carried out over a set of benchmarks for embedded multimedia applications, have demonstrated an average accuracy of 5% of the instruction-level estimation engine with respect to the RTL engine, with an average speed-up of four orders of magnitude.

A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems

SILVANO, CRISTINA;ZACCARIA, VITTORIO;
2002

Abstract

This paper describes a technique for modeling and estimating the power consumptionat the system-level for embedded VLIW (Very Long Instruction Word) architectures. The method is based on a hierarchy of dynamic power estimation engines: from the instruction-level down to the gate/transistor-level. Power macro-models have been developed for the main components of the system: theVLIW core, the register file, the instruction and data caches. The main goals to define a system-level simulation framework for the dynamic profiling of the power behavior during the software execution, providing also a break-down of the power contributions due to the single components of the system. The proposed approach has been applied to the Lx family of scalable embedded VLIWprocessors, jointly designed by STMicroelectronics and HPLabs. Experimental results, carried out over a set of benchmarks for embedded multimedia applications, have demonstrated an average accuracy of 5% of the instruction-level estimation engine with respect to the RTL engine, with an average speed-up of four orders of magnitude.
Microprocessor Architctures, VLIW Architectures, Embedded systems, Power Modeling and Estimation,
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/557600
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