This paper introduces an application mapping methodology and case study for multi-processor on-chip architectures. Starting from the description of an application in standard sequential code (e.g. in C), first the application is profiled, parallelized when possible, then its components are moved to hardware implementation when necessary to satisfy performance and power constraints. The key contribution of this work is a methodology for high-level hardware/software partitioning that allows the designer to use the same code for both hardware and software models for simulation, providing nevertheless preliminary estimations for timing and power consumption. The methodology has been applied to the coexploration of an industrial case study: an MPEG4 VGA realtime encoder.

An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures

BELTRAME, GIOVANNI;SCIUTO, DONATELLA;SILVANO, CRISTINA;
2006-01-01

Abstract

This paper introduces an application mapping methodology and case study for multi-processor on-chip architectures. Starting from the description of an application in standard sequential code (e.g. in C), first the application is profiled, parallelized when possible, then its components are moved to hardware implementation when necessary to satisfy performance and power constraints. The key contribution of this work is a methodology for high-level hardware/software partitioning that allows the designer to use the same code for both hardware and software models for simulation, providing nevertheless preliminary estimations for timing and power consumption. The methodology has been applied to the coexploration of an industrial case study: an MPEG4 VGA realtime encoder.
Proc. IFIP Fourteenth International Conference on Very Large Scale Integration - IFIP VLSI-SOC 2006
3901882197
Computer Architectures, Systems-on-Chip,
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/259181
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