Application specific multi-processor systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned either at design-time or at run-time, to provide the best trade-offs in terms of the selected system figures of merit (such as power and throughput) for a dynamic application-specific workload. Among the design-time (hardware) configurable parameters we can find the memory sub-system configuration (e.g. cache size and associativity) and other architectural parameters such as the instruction-level parallelism of the system processors. Among the run-time (software) configurable parameters we can find the overall degree of task-level parallelism associated with each application running on the chip. Typically, while the design-time exploration is performed in the early development stages for a set of static parameters, the tuning of the run-time parameters is performed dynamically by a run-time management software module after the system has been deployed. In this paper, we introduce a methodology for identifying a hardware configuration which is robust with respect to the variable workload scenario introduced by the run-time management. Moreover, the proposed methodology is aimed at providing useful information about the optimal operating points of the applications in terms of task-level parallelism. The proposed methodology is based on the NSGA-II evolutionary heuristic algorithm assisted by an artificial neural network (ANN). We then introduce a run-time management policy capable to exploit the above information to maximize the performance of the system under power budget constraints. Experimental results show that the proposed technique is able to reduce the overall design space exploration time yet providing a near-optimal solution, in terms of hardware parameters, to enable an innovative and efficient run-time management policy.

A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip

PALERMO, GIANLUCA;SILVANO, CRISTINA;ZACCARIA, VITTORIO
2009-01-01

Abstract

Application specific multi-processor systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned either at design-time or at run-time, to provide the best trade-offs in terms of the selected system figures of merit (such as power and throughput) for a dynamic application-specific workload. Among the design-time (hardware) configurable parameters we can find the memory sub-system configuration (e.g. cache size and associativity) and other architectural parameters such as the instruction-level parallelism of the system processors. Among the run-time (software) configurable parameters we can find the overall degree of task-level parallelism associated with each application running on the chip. Typically, while the design-time exploration is performed in the early development stages for a set of static parameters, the tuning of the run-time parameters is performed dynamically by a run-time management software module after the system has been deployed. In this paper, we introduce a methodology for identifying a hardware configuration which is robust with respect to the variable workload scenario introduced by the run-time management. Moreover, the proposed methodology is aimed at providing useful information about the optimal operating points of the applications in terms of task-level parallelism. The proposed methodology is based on the NSGA-II evolutionary heuristic algorithm assisted by an artificial neural network (ANN). We then introduce a run-time management policy capable to exploit the above information to maximize the performance of the system under power budget constraints. Experimental results show that the proposed technique is able to reduce the overall design space exploration time yet providing a near-optimal solution, in terms of hardware parameters, to enable an innovative and efficient run-time management policy.
Proceedings of IEEE 7th Symposium on Application Specific Processors, 2009. SASP '09.
9781424449392
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/544259
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