RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

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Mostrati risultati da 1 a 50 di 182
Titolo Data di pubblicazione Autori File
A formal methodology for automatic synthesis of Neural Nets 1-gen-1991 STORTI GAJANI, GIANCARLOFORNACIARI, WILLIAMSALICE, FABIO
Automatic synthesis of digital neural architectures 1-gen-1991 FORNACIARI, WILLIAMSALICE, FABIOSTORTI GAJANI, GIANCARLO
A Low Latency Digital Neural Network Architecture 1-gen-1992 FORNACIARI, WILLIAMSALICE, FABIO
A Structured Approach for Automatic Design of PN-based Digital Neural Netwoks 1-gen-1992 FORNACIARI, WILLIAMSALICE, FABIO
System level policies for fault tolerance issues in the FERMI project 1-gen-1993 ALIPPI, CESAREBREVEGLIERI, LUCA ODDONEDADDA, LUIGIPIURI, VINCENZOSALICE, FABIOSAMI, MARIAGIOVANNASTEFANELLI, RENATO +
A digital front-end and readout microsystem for calorimetry at LHC 1-gen-1993 ALIPPI, CESAREBREVEGLIERI, LUCA ODDONEDADDA, LUIGIPIURI, VINCENZOSALICE, FABIOSAMI, MARIAGIOVANNASTEFANELLI, RENATO +
A VSLI Macrocell Implementation for Digital Neural Nets 1-gen-1994 FORNACIARI, WILLIAMSALICE, FABIO
FERMI - A new generation of electronic modules for large data acquisition arrays required for high energy physics 1-gen-1994 ALIPPI, CESAREBREVEGLIERI, LUCA ODDONEDADDA, LUIGIPIURI, VINCENZOSALICE, FABIOSAMI, MARIAGIOVANNASTEFANELLI, RENATO +
Paradigmi Neurali e Tecniche Realizzative 1-gen-1994 FORNACIARI, WILLIAMPIURI, VINCENZOSTEFANELLI, RENATOSALICE, FABIO
FERMI - A new generation of electronic modules for large data acquisition arrays required for high energy physics 1-gen-1994 ALIPPI, CESAREBREVEGLIERI, LUCA ODDONEDADDA, LUIGIPIURI, VINCENZOSALICE, FABIOSAMI, MARIAGIOVANNASTEFANELLI, RENATO +
An Automatic VSLI Implementation of Hopfield ANNs 1-gen-1994 FORNACIARI, WILLIAMSALICE, FABIO
A Deterministic Constraint Driven Placement methodology for Analog Circuits 1-gen-1995 BRANDOLESE, CARLOPILLAN, MARGHERITASALICE, FABIOSCIUTO, DONATELLA
A BDD based algorithm for detecting difficult faults 1-gen-1995 BOLCHINI, CRISTIANASALICE, FABIO +
Digital VLSI Implementation of ANNs: a Cost-Effective Approach , In proc. of , December 18-20, 1995, pp.21 24. 1-gen-1995 FORNACIARI, WILLIAMSALICE, FABIO +
A General Criterion for Cost-driven realization of Digital ANNs 1-gen-1995 FORNACIARI, WILLIAMSALICE, FABIO +
A state encoding for self-checking finite state machines 1-gen-1995 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
Self-checking FSMs based on a constant distance state encoding 1-gen-1995 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
Behavior-driven minimal implementation of digital ANNs 1-gen-1995 FORNACIARI, WILLIAMSALICE, FABIO +
Behavior of self-checking checkers for 1-out-of-3 codes based on pass-transistor logic 1-gen-1995 SALICE, FABIOSCIUTO, DONATELLA +
A new architecture for the automatic design of custom digital neural network 1-gen-1995 FORNACIARI, WILLIAMSALICE, FABIO
Correct Implementation of Digital Neural Networks 1-gen-1995 FORNACIARI, WILLIAMSALICE, FABIO +
A Constraint Generation Tool for the Design of High Frequency Integrated Cirsuits 1-gen-1996 PILLAN, MARGHERITASALICE, FABIO +
Redundant faults in TSC networks: definition and removal 1-gen-1996 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Analog circuits placement: A constraint driven methodology 1-gen-1996 BRANDOLESE, CARLOPILLAN, MARGHERITASALICE, FABIOSCIUTO, DONATELLA
Struttura e progetto dei calcolatori : l'interfaccia hardware software 1-gen-1996 FORNACIARI, WILLIAMSALICE, FABIO +
Design of Totally Self Checking Checkers for a Class of Constant Hamming Distance Codes 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Conditions for the design of circuits with concurrent error detection properties 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
A two-level cosimulation environment 1-gen-1997 FORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
Improving design turnaround time via two-levels Hw/Sw co-simulation 1-gen-1997 FORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA +
Designing networks with error detection properties through the fault-error relation 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
A flexible model for evaluating the behavior of hardware/software systems 1-gen-1997 FORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA +
A scalar cost function for analyzing the quality of totally self-checking design methodologies 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
La proposta Seed per i sistemi embedded - parte seconda 1-gen-1997 SALICE, FABIOFORNACIARI, WILLIAM +
La proposta Seed per i sistemi embedded - parte prima 1-gen-1997 SALICE, FABIOFORNACIARI, WILLIAM +
A novel methodology for designing TSC networks based on the parity bit code 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Parity bit code: achieving a complete fault coverage in the design of TSC combinational networks 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Special Purpose Neurocomputers: An Automatic Design Approach 1-gen-1997 FORNACIARI, WILLIAMSALICE, FABIO +
A TSC evaluation function for combinational circuits 1-gen-1997 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
From behavior to VHDL: a CAD environment for SPNNs 1-gen-1998 FORNACIARI, WILLIAMPIURI, VINCENZOSALICE, FABIO
A Case Study in Co-Design: Reengineering an Industrial Device 1-gen-1998 FORNACIARI, WILLIAMSALICE, FABIO +
High Level Synthesis for Concurrent Error Detection 1-gen-1998 BOLCHINI, CRISTIANAFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
A Template-Based Strategy for Mapping System Level Specification onto VHDL Hardware Modules September 6-11, 1998. pp. 139-146. 1-gen-1998 FORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA +
System-level performance estimation strategy for Sw and Hw 1-gen-1998 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA +
A model for system-level timed analysis and profiling 1-gen-1998 FORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA +
Fault analysis in networks with concurrent error detection properties 1-gen-1998 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Fault Analysis for Networks with Concurrent Error Detection Properties 1-gen-1998 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Concurrent error detection at architectural level 1-gen-1998 BOLCHINI, CRISTIANAFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
Evaluation of VHDL Based Design Reuse Through lambda-Block Analysis 1-gen-1999 FORNACIARI, WILLIAMSALICE, FABIO +
Reti di calcolatori 1-gen-1999 BREVEGLIERI, LUCA ODDONEFORNACIARI, WILLIAMSALICE, FABIO
A synthesis methodology aimed at improving the quality of TSC devices 1-gen-1999 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
Mostrati risultati da 1 a 50 di 182
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