The design of an embedded system is a process where the timing of the architecture should rake into account both the functionality and the timing performance while considering the heterogeneity of the hw and sw components. The goal of this paper is to present the new model developed during the SEED Esprit project, to estimate the software and hardware characteristics for cosimulation and profiling within the TOSCA codesign framework. The impact on the design space exploration of such an high-level cosimulation strategy has been tested by considering as a benchmark the reengineering of an industrial device.
System-level performance estimation strategy for Sw and Hw
BRANDOLESE, CARLO;FORNACIARI, WILLIAM;SALICE, FABIO;SCIUTO, DONATELLA
1998-01-01
Abstract
The design of an embedded system is a process where the timing of the architecture should rake into account both the functionality and the timing performance while considering the heterogeneity of the hw and sw components. The goal of this paper is to present the new model developed during the SEED Esprit project, to estimate the software and hardware characteristics for cosimulation and profiling within the TOSCA codesign framework. The impact on the design space exploration of such an high-level cosimulation strategy has been tested by considering as a benchmark the reengineering of an industrial device.File in questo prodotto:
File | Dimensione | Formato | |
---|---|---|---|
System-level_performance_estimation_strategy_for_sw_and_hw.pdf
accesso aperto
:
Publisher’s version
Dimensione
68.68 kB
Formato
Adobe PDF
|
68.68 kB | Adobe PDF | Visualizza/Apri |
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.