Improving design turnaround time via two-levels Hw/Sw co-simulation

Steady growing in demand of fast turnaround time is going to shift as much as possible the system tuning from the physical prototyping to the virtual prototyping. The paper proposes a novel approach for mixed hw-sw implementation of embedded systems, allowing high-level simulation of the overall architecture as well as a deeper analysis of timing performance by exploiting commercial VHDL CAD tools, At the higher level, functional debug and tradeoff analysis is performed on a OCCAM-based system-level model, at the lower level a VHDL-based description for both the hw and the sw is built for the fine grain verification of the system, The peeper introduces the hva levels of simulation, showing their impact in terms of design flow management and design time.