The chapter presents a methodology to be used for both design and analysis of digital systems described by using VHDL. The developed CAD environment allows the designer to inspect the code of existing systems in order to extract candidate functionality suitable for reuse as well as to evaluate the quality of VHDL in a reuse perspective. The proposed methodology has been validated by considering small industrial benchmarks and by redesigning an industrial core cell, a PC-Card interface, used in commercial devices.
|Titolo:||Evaluation of VHDL Based Design Reuse Through lambda-Block Analysis|
|Data di pubblicazione:||1999|
|Appare nelle tipologie:||04.1 Contributo in Atti di convegno|