This paper presents an automatic design flow for digital special purpose feed-forward multi-layer neural networks (SPNNs). The target architecture is constituted by a collection of basic elements called Pseudo-Neurons (PNs) connected in a pipelined-tree manner, to suit efficient VLSI implementation and, due to an internal pipelined multiprocessing, achieving low latency and good throughput. The related CAD environment implements three successive stages: the weights discretization (WD), the architectural synthesis (AS), and the VHDL model generation (VHDL_G).

From behavior to VHDL: a CAD environment for SPNNs

FORNACIARI, WILLIAM;PIURI, VINCENZO;SALICE, FABIO
1998-01-01

Abstract

This paper presents an automatic design flow for digital special purpose feed-forward multi-layer neural networks (SPNNs). The target architecture is constituted by a collection of basic elements called Pseudo-Neurons (PNs) connected in a pipelined-tree manner, to suit efficient VLSI implementation and, due to an internal pipelined multiprocessing, achieving low latency and good throughput. The related CAD environment implements three successive stages: the weights discretization (WD), the architectural synthesis (AS), and the VHDL model generation (VHDL_G).
Neural Nets WIRN VIETRI-98
978-1-4471-0811-5
978-1-4471-1208-2
Synaptic Weights, Very Large Scale Integration, Delay Cell, Sigmoidal Activation Function, Architectural Parameter
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/693861
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