From behavior to VHDL: a CAD environment for SPNNs

This paper presents an automatic design flow for digital special purpose feed-forward multi-layer neural networks (SPNNs). The target architecture is constituted by a collection of basic elements called Pseudo-Neurons (PNs) connected in a pipelined-tree manner, to suit efficient VLSI implementation and, due to an internal pipelined multiprocessing, achieving low latency and good throughput. The related CAD environment implements three successive stages: the weights discretization (WD), the architectural synthesis (AS), and the VHDL model generation (VHDL_G).