Control-dominated architectures are usually specify, in a hardware description language (HDL), by means of a composition of FSMs. This paper presents two FSMs based models which can be extracted from a Statechart or a HDL description. Such models are compared to the description of the device at the different abstraction levels of a standard synthesis pow. This comparison simplifies the testing problem producing a complete testing strategy that uses functional information to perform scan insertion, redundancies removal and test pattern generation even for such devices which cannot be satisfactorily analyzed at the gate level.

A complete test strategy based on interacting and hierarchical FSMs

SCIUTO, DONATELLA
1997-01-01

Abstract

Control-dominated architectures are usually specify, in a hardware description language (HDL), by means of a composition of FSMs. This paper presents two FSMs based models which can be extracted from a Statechart or a HDL description. Such models are compared to the description of the device at the different abstraction levels of a standard synthesis pow. This comparison simplifies the testing problem producing a complete testing strategy that uses functional information to perform scan insertion, redundancies removal and test pattern generation even for such devices which cannot be satisfactorily analyzed at the gate level.
Proceedings of the 1997 IEEE International Symposium on Circuits and Systems (ISCAS 97) - Circuits and Systems in the Information Age
078033583X
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/666804
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