RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

TUMEO, ANTONINO

TUMEO, ANTONINO  

DIPARTIMENTO DI ELETTRONICA E INFORMAZIONE (attivo dal 01/01/1900 al 31/12/2012)  

Mostra records
Risultati 1 - 20 di 41 (tempo di esecuzione: 0.035 secondi).
Titolo Data di pubblicazione Autori File
A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA 1-gen-2007 FERRANDI, FABRIZIOMONCHIERO, MATTEOPALERMO, GIANLUCASCIUTO, DONATELLATUMEO, ANTONINO
A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries 1-gen-2016 CASTELLANA, VITO GIOVANNITUMEO, ANTONINOFERRANDI, FABRIZIOLATTUADA, MARCO +
A dynamically scheduled architecture for the synthesis of graph methods 1-gen-2016 MINUTOLI, MARCOCASTELLANA, VITO GIOVANNITUMEO, ANTONINOLATTUADA, MARCOFERRANDI, FABRIZIO
A multiprocessor self-reconfigurable jpeg2000 encoder 1-gen-2009 TUMEO, ANTONINOMONCHIERO, MATTEOPALERMO, GIANLUCAFERRANDI, FABRIZIOSCIUTO, DONATELLA +
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs 1-gen-2007 FERRANDI, FABRIZIOMONCHIERO, MATTEOPALERMO, GIANLUCASCIUTO, DONATELLATUMEO, ANTONINO
A reconfigurable multiprocessor architecture for a reliable face recognition implementation 1-gen-2010 TUMEO, ANTONINOPALERMO, GIANLUCAFERRANDI, FABRIZIOSCIUTO, DONATELLA +
Accelerating Data Processing at the Edge with Extreme Specialization 1-gen-2022 ANTONINO TUMEOMARCO MINUTOLIVITO GIOVANNI CASTELLANASERENA CURZEL +
An Evolutionary Approach to Area-Time Optimization of FPGA designs 1-gen-2007 FERRANDI, FABRIZIOLANZI, PIER LUCAPALERMO, GIANLUCAPILATO, CHRISTIANSCIUTO, DONATELLATUMEO, ANTONINO
An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAs 1-gen-2007 FERRANDI, FABRIZIOMONCHIERO, MATTEOPALERMO, GIANLUCASCIUTO, DONATELLATUMEO, ANTONINO
An Interrupt Controller for FPGA-based Multiprocessors 1-gen-2007 FERRANDI, FABRIZIOMONCHIERO, MATTEOPALERMO, GIANLUCASCIUTO, DONATELLATUMEO, ANTONINO +
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 1-gen-2010 FERRANDI, FABRIZIOLANZI, PIER LUCAPILATO, CHRISTIANSCIUTO, DONATELLATUMEO, ANTONINO
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 1-gen-2008 TUMEO, ANTONINOPILATO, CHRISTIANFERRANDI, FABRIZIOSCIUTO, DONATELLALANZI, PIER LUCA
Ant Colony Optimization for Mapping, Scheduling and Placing in Reconfigurable Systems 1-gen-2013 FERRANDI, FABRIZIOLANZI, PIER LUCAPILATO, CHRISTIANSCIUTO, DONATELLATUMEO, ANTONINO
Automatic parallelization of sequential specifications for symmetric MPSoCs 1-gen-2007 FERRANDI, FABRIZIOFOSSATI, LUCALATTUADA, MARCOPALERMO, GIANLUCASCIUTO, DONATELLATUMEO, ANTONINO
Considerations on the use of custom accelerators for big data analytics 1-gen-2017 Castellana, Vito GiovanniTumeo, AntoninoMinutoli, MarcoLattuada, MarcoFerrandi, Fabrizio
Efficient synthesis of graph methods: a dynamically scheduled architecture 1-gen-2016 CASTELLANA, VITO GIOVANNITUMEO, ANTONINOLATTUADA, MARCOFERRANDI, FABRIZIO +
Enabling the high level synthesis of data analytics accelerators 1-gen-2016 CASTELLANA, VITO GIOVANNITUMEO, ANTONINOLATTUADA, MARCOFERRANDI, FABRIZIO +
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems 1-gen-2009 FERRANDI, FABRIZIOLANZI, PIER LUCAPILATO, CHRISTIANSCIUTO, DONATELLATUMEO, ANTONINO +
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 1-gen-2007 FERRANDI, FABRIZIOLANZI, PIER LUCAPALERMO, GIANLUCAPILATO, CHRISTIANSCIUTO, DONATELLATUMEO, ANTONINO
Function Proxies for Improved Resource Sharing in High Level Synthesis 1-gen-2015 CASTELLANA, VITO GIOVANNITUMEO, ANTONINOFERRANDI, FABRIZIO +