RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ZACCARIA, VITTORIO
 Distribuzione geografica
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Continente #
NA - Nord America 8.754
EU - Europa 3.364
AS - Asia 2.898
SA - Sud America 600
AF - Africa 117
OC - Oceania 4
Continente sconosciuto - Info sul continente non disponibili 2
Totale 15.739
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Nazione #
US - Stati Uniti d'America 8.619
RU - Federazione Russa 1.384
SG - Singapore 957
CN - Cina 770
BR - Brasile 504
VN - Vietnam 476
IT - Italia 348
UA - Ucraina 282
SE - Svezia 259
DE - Germania 228
KR - Corea 178
GB - Regno Unito 160
FR - Francia 157
FI - Finlandia 143
JP - Giappone 114
CA - Canada 109
AT - Austria 104
HK - Hong Kong 92
IN - India 77
IE - Irlanda 70
NL - Olanda 67
ES - Italia 64
MA - Marocco 62
BD - Bangladesh 34
JO - Giordania 34
AR - Argentina 31
PL - Polonia 27
EC - Ecuador 23
ID - Indonesia 23
BE - Belgio 20
IQ - Iraq 20
ZA - Sudafrica 19
VE - Venezuela 18
PH - Filippine 16
TR - Turchia 15
MX - Messico 14
UZ - Uzbekistan 13
PK - Pakistan 12
SA - Arabia Saudita 11
TW - Taiwan 10
PY - Paraguay 9
CH - Svizzera 7
CI - Costa d'Avorio 7
CL - Cile 7
LT - Lituania 7
TH - Thailandia 7
AE - Emirati Arabi Uniti 6
BG - Bulgaria 6
DZ - Algeria 6
KE - Kenya 6
AZ - Azerbaigian 5
BJ - Benin 5
NP - Nepal 5
RO - Romania 5
AU - Australia 4
EG - Egitto 4
LB - Libano 4
OM - Oman 4
PT - Portogallo 4
BH - Bahrain 3
CO - Colombia 3
CR - Costa Rica 3
CZ - Repubblica Ceca 3
GR - Grecia 3
IL - Israele 3
IR - Iran 3
PE - Perù 3
AL - Albania 2
BO - Bolivia 2
DO - Repubblica Dominicana 2
ET - Etiopia 2
EU - Europa 2
KG - Kirghizistan 2
MD - Moldavia 2
MU - Mauritius 2
RS - Serbia 2
SN - Senegal 2
AD - Andorra 1
BB - Barbados 1
BS - Bahamas 1
BY - Bielorussia 1
EE - Estonia 1
GA - Gabon 1
GI - Gibilterra 1
GT - Guatemala 1
HU - Ungheria 1
JM - Giamaica 1
LK - Sri Lanka 1
LV - Lettonia 1
ME - Montenegro 1
MK - Macedonia 1
NI - Nicaragua 1
NO - Norvegia 1
PA - Panama 1
PS - Palestinian Territory 1
SK - Slovacchia (Repubblica Slovacca) 1
SY - Repubblica araba siriana 1
TM - Turkmenistan 1
TN - Tunisia 1
TT - Trinidad e Tobago 1
Totale 15.739
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Città #
Ashburn 1.220
Fairfield 1.030
Woodbridge 674
Houston 598
San Jose 575
Singapore 541
Seattle 463
Chandler 423
Wilmington 393
Cambridge 386
Ann Arbor 319
Santa Clara 218
Moscow 206
Beijing 191
Seoul 170
The Dalles 158
Jacksonville 157
Boardman 135
Council Bluffs 132
Hefei 129
Dearborn 122
Dallas 121
Tokyo 106
Dong Ket 97
Medford 94
Vienna 93
Lawrence 92
Los Angeles 87
Lauterbourg 84
Hanoi 80
Ottawa 80
North Charleston 74
Milan 73
Dublin 70
Hong Kong 68
Ho Chi Minh City 65
San Diego 58
São Paulo 52
Málaga 44
Helsinki 42
New York 42
Des Moines 38
Buffalo 35
Amman 33
Kenitra 31
Amsterdam 29
Frankfurt am Main 28
Casablanca 27
London 24
Las Vegas 23
Orem 21
Brussels 20
Warsaw 20
Guangzhou 19
Shanghai 19
Stockholm 18
Chicago 17
Rio de Janeiro 17
Brooklyn 16
Montreal 16
Belo Horizonte 14
Da Nang 14
Turku 14
Auburn Hills 13
Chennai 13
Denver 13
Mountain View 13
Nuremberg 13
Jakarta 12
Kent 12
Norwalk 12
Tashkent 12
Tianjin 12
Columbus 11
Haiphong 11
Hangzhou 11
Johannesburg 10
Lucca 10
Redondo Beach 10
Verona 10
Curitiba 9
Guayaquil 9
Poplar 9
Taipei 9
Düsseldorf 8
Indiana 8
Phoenix 8
Wuhan 8
Abidjan 7
Brasília 7
Falls Church 7
Munich 7
Redwood City 7
Washington 7
Aracaju 6
Caracas 6
Dhaka 6
Elk Grove Village 6
Erbil 6
Ha Kwai Chung 6
Totale 10.599
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Nome #
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 287
A Design Framework to Efficiently Explore Energy-Delay Tradeoffs 251
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 244
AES power attack based on induced cache miss and countermeasure 241
DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling 241
A System-Level Methodology for Fast Multi-Objective Design Space Exploration 237
A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems 234
About the performances of the advanced encryption standard in embedded systems with cache memory 230
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis 227
A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip 226
Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering 213
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 211
OpenCL application auto-tuning and run-time resource management for multi-core platforms 211
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach 210
A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip 207
Combining application adaptivity and system-wide Resource Management on multi-core platforms 207
Branch Prediction Techniques for Low-Power VLIW Processors 206
An instruction-level methodology for power estimation and optimization of embedded VLIW cores 203
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 203
Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints 200
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods 196
A framework for Compiler Level statistical analysis over customized VLIW architecture 194
Parallel paradigms and run-time management techniques for many-core architectures: the 2parma approach 193
On the Role of Context in the Design of Mobile Mashups 193
Design Space Exploration Supporting Run-time Resource Management 193
A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization 192
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems 190
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures 190
Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures 187
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems 187
An Instruction-Level Energy Model for Embedded VLIW Architectures 186
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 180
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications 179
Parallel paradigms and run-time management techniques for many-core architectures 178
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures 177
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models 174
A Power Modeling and Estimation Framework for VLIW-based Embedded Systems 171
Symbolic Analysis of Higher-Order Side Channel Countermeasures 171
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors 169
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration 169
Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips 168
An Agent-based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems 167
Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models 165
ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems 160
On the spectral features of robust probing security 160
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip 158
ADD-based Spectral Analysis of Probing Security 157
Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics 156
Low-Power Data Forwarding for VLIW Embedded Architectures 154
Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems 153
Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming 151
Conversational Data Exploration 151
MULTICUBE: Multi-objective design space exploration of multi-core architectures 150
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling 148
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach 146
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 145
Instruction-Level Power Estimation for Embedded VLIW Cores 144
A power attack methodology to AES based on induced cache misses: procedure, evaluation and possible countermeasures 144
Context-aware access to heterogeneous resources through on-the-fly mashups 144
Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques 143
Power Exploration for Embedded VLIW Architectures 142
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture 140
Robust Optimization of SoC Architectures: A Multi-Scenario Approach 138
Multi-Objective Design Space Exploration of Embedded Systems 134
The MULTICUBE Design Flow 131
Darth's Saber: A Key Exfiltration Attack for Symmetric Ciphers Using Laser Light 131
Energy-Performance Design Space Exploration of SMT Architectures Exploiting Selective Load Value Predictions 130
A relation calculus for reasoning about t-probing security 128
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction 128
An industrial design space exploration framework for supporting run-time resource management on multi-core systems 127
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures 127
OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces 125
Design-space exploration and runtime resource management for multicores 123
CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks 122
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration 120
Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors 119
Power-Performance System-Level Exploration of a MicroSPARC2-based Embedded Architecture 118
How might the iPad change healthcare? 117
Optimization Algorithms for Design Space Exploration of Embedded Systems 117
Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors 117
Design Space Exploration of Parallel Architectures 112
Reducing the complexity of instruction-level power models for VLIW processors 110
Power Reduction on VLIW Processors through Data Forwarding 107
Spectral Features of Higher-Order Side-Channel Countermeasures 107
ConceptOS: A Micro-Kernel Approach to Firmware Updates of Always-On Resource-Constrained Hubris-Based IoT Systems 105
Efficient Attack-Surface Exploration for Electromagnetic Fault Injection 104
An F-algebra for analysing information leaks in the presence of glitches 104
Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration 102
On robust strong-non-interferent low-latency multiplications 102
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip 100
Processor architecture with variable-stage pipeline 99
Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product 98
Processor Architecture 96
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 95
Response Surface Modeling for Design Space Exploration of Embedded Systems 95
Toward truly personal chatbots: On the Development of Custom Conversational Assistants 92
Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework 92
Layer-wise Exploration of a Neural Processing Unit Compiler's Optimization Space 89
An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks 85
Low Effort, High Accuracy Network-on-Chip Power Macro ModelingIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 72
Totale 15.722
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Categoria #
all - tutte 44.257
article - articoli 10.497
book - libri 377
conference - conferenze 28.582
curatela - curatele 0
other - altro 0
patent - brevetti 821
selected - selezionate 0
volume - volumi 3.694
Totale 88.228
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021336 0 0 0 0 0 0 0 0 0 0 99 237
2021/2022863 30 151 64 34 111 49 50 53 38 43 88 152
2022/2023945 120 81 19 132 105 125 7 68 144 65 60 19
2023/2024424 32 91 27 39 40 46 19 32 0 21 5 72
2024/20251.699 14 57 49 28 276 110 63 181 224 128 281 288
2025/20266.110 1.081 1.095 295 489 358 381 1.088 312 343 619 49 0
Totale 15.823