RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ZACCARIA, VITTORIO
 Distribuzione geografica
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Continente #
NA - Nord America 6.120
EU - Europa 1.526
AS - Asia 519
AF - Africa 13
SA - Sud America 4
Continente sconosciuto - Info sul continente non disponibili 2
OC - Oceania 2
Totale 8.186
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Nazione #
US - Stati Uniti d'America 6.037
IT - Italia 306
UA - Ucraina 271
SE - Svezia 245
VN - Vietnam 193
DE - Germania 165
SG - Singapore 154
FI - Finlandia 125
GB - Regno Unito 112
AT - Austria 99
CN - Cina 88
CA - Canada 83
IE - Irlanda 66
ES - Italia 51
IN - India 33
JO - Giordania 29
NL - Olanda 26
BE - Belgio 19
FR - Francia 17
KR - Corea 7
BJ - Benin 5
CI - Costa d'Avorio 5
BG - Bulgaria 4
CH - Svizzera 3
PL - Polonia 3
RU - Federazione Russa 3
AR - Argentina 2
AU - Australia 2
EU - Europa 2
GR - Grecia 2
ID - Indonesia 2
IQ - Iraq 2
JP - Giappone 2
MU - Mauritius 2
RO - Romania 2
AL - Albania 1
BR - Brasile 1
CL - Cile 1
EE - Estonia 1
HK - Hong Kong 1
HU - Ungheria 1
IL - Israele 1
IR - Iran 1
LB - Libano 1
LK - Sri Lanka 1
LT - Lituania 1
LV - Lettonia 1
NO - Norvegia 1
OM - Oman 1
PH - Filippine 1
PK - Pakistan 1
PT - Portogallo 1
TR - Turchia 1
ZA - Sudafrica 1
Totale 8.186
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Città #
Fairfield 1.030
Woodbridge 673
Houston 593
Ashburn 513
Seattle 463
Chandler 423
Wilmington 393
Cambridge 386
Ann Arbor 319
Jacksonville 157
Boardman 135
Dearborn 122
Singapore 110
Dong Ket 97
Medford 94
Lawrence 92
Vienna 92
Ottawa 80
Dublin 66
Milan 62
San Diego 57
Málaga 44
Helsinki 40
Beijing 38
Des Moines 37
Amman 29
Amsterdam 19
Brussels 19
New York 18
Auburn Hills 13
Mountain View 13
Norwalk 12
Shanghai 12
Columbus 10
Lucca 10
Verona 10
London 9
Dallas 8
Indiana 8
Falls Church 7
Redwood City 7
Abidjan 5
Cotonou 5
Los Angeles 5
Miami 5
Seongnam 5
Washington 5
Falkenstein 4
Kilburn 4
Klagenfurt 4
Kunming 4
Stockholm 4
Chiswick 3
Graz 3
Grenoble 3
Groningen 3
Hefei 3
Kaisheim 3
Livorno 3
Medina 3
Prescot 3
Redmond 3
Tappahannock 3
Warsaw 3
Acton 2
Bangalore 2
Barcelona 2
Bergamo 2
Bern 2
Bochum 2
Bologna 2
Cesa 2
College Park 2
Como 2
Edinburgh 2
Florence 2
Greenbelt 2
Guangzhou 2
Jinan 2
Meda 2
Munich 2
Nanchang 2
Nanjing 2
Nuremberg 2
Pioltello 2
Pontassieve 2
Pordenone 2
Reggio Emilia 2
Rome 2
San Michele Al Tagliamento 2
Santa Clara 2
St Louis 2
Taranto 2
Torre Del Greco 2
Tres Cantos 2
Vigevano 2
Whyteleafe 2
Wuhan 2
Aachen 1
Abbiategrasso 1
Totale 6.476
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Nome #
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis 163
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 151
Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering 145
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures. 141
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods 138
A System-Level Methodology for Fast Multi-Objective Design Space Exploration 133
Branch Prediction Techniques for Low-Power VLIW Processors 133
Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures 131
Design Space Exploration Supporting Run-time Resource Management 131
A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems 128
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures 126
DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling 124
AES power attack based on induced cache miss and countermeasure 123
A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip 123
About the performances of the advanced encryption standard in embedded systems with cache memory 120
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration 118
A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip 114
An instruction-level methodology for power estimation and optimization of embedded VLIW cores 113
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors 112
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models 112
A Design Framework to Efficiently Explore Energy-Delay Tradeoffs 111
ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems 109
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip 108
On the Role of Context in the Design of Mobile Mashups 108
Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics 107
Robust Optimization of SoC Architectures: A Multi-Scenario Approach 105
Parallel paradigms and run-time management techniques for many-core architectures: 2parma approach 103
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach 103
Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips 101
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems 100
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 100
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 99
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 98
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture 97
OpenCL application auto-tuning and run-time resource management for multi-core platforms 97
An Instruction-Level Energy Model for Embedded VLIW Architectures 96
Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming 95
A framework for Compiler Level statistical analysis over customized VLIW architecture 95
Symbolic Analysis of Higher-Order Side Channel Countermeasures 95
Combining application adaptivity and system-wide Resource Management on multi-core platforms 95
A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization 94
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach 93
Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques 92
Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints 92
Power Exploration for Embedded VLIW Architectures 90
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures 90
Instruction-Level Power Estimation for Embedded VLIW Cores 89
Low-Power Data Forwarding for VLIW Embedded Architectures 89
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems 88
Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems 87
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 87
Parallel paradigms and run-time management techniques for many-core architectures 87
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications 86
OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces 83
Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models 81
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction 80
An Agent-based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems 80
An industrial design space exploration framework for supporting run-time resource management on multi-core systems 78
Conversational Data Exploration 78
Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors 77
Multi-Objective Design Space Exploration of Embedded Systems 75
Energy-Performance Design Space Exploration of SMT Architectures Exploiting Selective Load Value Predictions 75
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures 74
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling 72
The MULTICUBE Design Flow 70
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration 69
How might the iPad change healthcare? 69
Power-Performance System-Level Exploration of a MicroSPARC2-based Embedded Architecture 68
MULTICUBE: Multi-objective design space exploration of multi-core architectures 68
A Power Modeling and Estimation Framework for VLIW-based Embedded Systems 64
Design Space Exploration of Parallel Architectures 62
Reducing the complexity of instruction-level power models for VLIW processors 62
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip 61
Context-aware access to heterogeneous resources through on-the-fly mashups 60
Design-space exploration and runtime resource management for multicores 60
Optimization Algorithms for Design Space Exploration of Embedded Systems 56
Darth's Saber: A Key Exfiltration Attack for Symmetric Ciphers Using Laser Light 54
On the spectral features of robust probing security 54
Power Reduction on VLIW Processors through Data Forwarding 53
CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks 53
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 52
Spectral Features of Higher-Order Side-Channel Countermeasures 51
Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration 50
Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework 46
Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors 44
Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product 44
An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks 41
A power attack methodology to AES based on induced cache misses: procedure, evaluation and possible countermeasures 39
Processor architecture with variable-stage pipeline 38
Response Surface Modeling for Design Space Exploration of Embedded Systems 38
An F-algebra for analysing information leaks in the presence of glitches 35
Processor Architecture 34
null 29
Toward truly personal chatbots: On the Development of Custom Conversational Assistants 27
ADD-based Spectral Analysis of Probing Security 26
On robust strong-non-interferent low-latency multiplications 18
A relation calculus for reasoning about t-probing security 16
Low Effort, High Accuracy Network-on-Chip Power Macro ModelingIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16
Efficient Attack-Surface Exploration for Electromagnetic Fault Injection 9
Interruptible Remote Attestation of Low-end IoT Microcontrollers via Performance Counters 6
Totale 8.260
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Categoria #
all - tutte 26.144
article - articoli 6.132
book - libri 225
conference - conferenze 17.018
curatela - curatele 0
other - altro 0
patent - brevetti 402
selected - selezionate 0
volume - volumi 2.230
Totale 52.151
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201.890 0 0 0 0 315 348 306 233 298 105 213 72
2020/20211.314 110 72 126 66 89 93 91 108 87 136 99 237
2021/2022863 30 151 64 34 111 49 50 53 38 43 88 152
2022/2023945 120 81 19 132 105 125 7 68 144 65 60 19
2023/2024424 32 91 27 39 40 46 19 32 0 21 5 72
2024/2025255 14 57 49 28 107 0 0 0 0 0 0 0
Totale 8.269