RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ZACCARIA, VITTORIO
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
NA - Nord America 8.978
EU - Europa 3.661
AS - Asia 2.932
SA - Sud America 606
AF - Africa 117
OC - Oceania 4
Continente sconosciuto - Info sul continente non disponibili 2
Totale 16.300
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 8.834
RU - Federazione Russa 1.384
SG - Singapore 960
CN - Cina 772
IT - Italia 635
BR - Brasile 506
VN - Vietnam 504
UA - Ucraina 282
SE - Svezia 261
DE - Germania 228
KR - Corea 178
GB - Regno Unito 160
FR - Francia 159
FI - Finlandia 143
JP - Giappone 114
CA - Canada 113
AT - Austria 104
HK - Hong Kong 92
IN - India 77
IE - Irlanda 70
NL - Olanda 67
ES - Italia 65
MA - Marocco 62
BD - Bangladesh 35
JO - Giordania 34
AR - Argentina 31
PL - Polonia 27
EC - Ecuador 24
ID - Indonesia 23
BE - Belgio 20
IQ - Iraq 20
ZA - Sudafrica 19
VE - Venezuela 18
PH - Filippine 16
MX - Messico 15
TR - Turchia 15
UZ - Uzbekistan 13
PK - Pakistan 12
SA - Arabia Saudita 11
CH - Svizzera 10
TW - Taiwan 10
PY - Paraguay 9
CI - Costa d'Avorio 7
CL - Cile 7
LT - Lituania 7
TH - Thailandia 7
AE - Emirati Arabi Uniti 6
BG - Bulgaria 6
DZ - Algeria 6
KE - Kenya 6
AZ - Azerbaigian 5
BJ - Benin 5
JM - Giamaica 5
NP - Nepal 5
PE - Perù 5
PT - Portogallo 5
RO - Romania 5
AU - Australia 4
CO - Colombia 4
EG - Egitto 4
LB - Libano 4
OM - Oman 4
BH - Bahrain 3
CR - Costa Rica 3
CZ - Repubblica Ceca 3
GR - Grecia 3
IL - Israele 3
IR - Iran 3
AL - Albania 2
BO - Bolivia 2
DO - Repubblica Dominicana 2
ET - Etiopia 2
EU - Europa 2
HU - Ungheria 2
KG - Kirghizistan 2
MD - Moldavia 2
MU - Mauritius 2
RS - Serbia 2
SN - Senegal 2
AD - Andorra 1
BB - Barbados 1
BS - Bahamas 1
BY - Bielorussia 1
EE - Estonia 1
GA - Gabon 1
GI - Gibilterra 1
GT - Guatemala 1
LK - Sri Lanka 1
LV - Lettonia 1
ME - Montenegro 1
MK - Macedonia 1
NI - Nicaragua 1
NO - Norvegia 1
PA - Panama 1
PS - Palestinian Territory 1
SK - Slovacchia (Repubblica Slovacca) 1
SY - Repubblica araba siriana 1
TM - Turkmenistan 1
TN - Tunisia 1
TT - Trinidad e Tobago 1
Totale 16.300
Salva come PNG Salva come JPEG
Città #
Ashburn 1.249
Fairfield 1.030
Woodbridge 674
Houston 598
San Jose 586
Singapore 544
Seattle 463
Chandler 423
Wilmington 395
Cambridge 386
Ann Arbor 319
Santa Clara 228
Moscow 206
Beijing 191
Milan 170
Seoul 170
The Dalles 158
Jacksonville 157
Council Bluffs 153
Boardman 146
Hefei 129
Dallas 128
Dearborn 122
Tokyo 106
Dong Ket 97
Medford 94
Vienna 93
Hanoi 92
Lawrence 92
Los Angeles 87
Lauterbourg 84
Ottawa 80
North Charleston 75
Dublin 70
Hong Kong 68
Ho Chi Minh City 67
San Diego 58
São Paulo 52
New York 48
Rome 45
Málaga 44
Helsinki 42
Des Moines 38
Buffalo 35
Amman 33
Kenitra 31
Amsterdam 29
Frankfurt am Main 28
Casablanca 27
Las Vegas 27
London 24
Orem 22
Brussels 20
Da Nang 20
Shanghai 20
Stockholm 20
Warsaw 20
Guangzhou 19
Brooklyn 18
Chicago 18
Rio de Janeiro 18
Montreal 16
Belo Horizonte 14
Turku 14
Auburn Hills 13
Chennai 13
Denver 13
Haiphong 13
Mountain View 13
Naples 13
Nuremberg 13
Jakarta 12
Kent 12
Lucca 12
Norwalk 12
Tashkent 12
Tianjin 12
Bologna 11
Columbus 11
Hangzhou 11
Turin 11
Verona 11
Johannesburg 10
Miami 10
Redondo Beach 10
Curitiba 9
Guayaquil 9
Phoenix 9
Poplar 9
Taipei 9
Düsseldorf 8
Florence 8
Indiana 8
Wuhan 8
Abidjan 7
Atlanta 7
Brasília 7
Falls Church 7
Munich 7
Redwood City 7
Totale 10.897
Salva come PNG Salva come JPEG
Nome #
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 293
A Design Framework to Efficiently Explore Energy-Delay Tradeoffs 253
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 253
DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling 250
AES power attack based on induced cache miss and countermeasure 244
A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems 243
A System-Level Methodology for Fast Multi-Objective Design Space Exploration 238
About the performances of the advanced encryption standard in embedded systems with cache memory 233
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis 232
A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip 229
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach 216
Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering 215
OpenCL application auto-tuning and run-time resource management for multi-core platforms 215
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 214
An instruction-level methodology for power estimation and optimization of embedded VLIW cores 212
Branch Prediction Techniques for Low-Power VLIW Processors 209
A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip 209
Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints 209
Combining application adaptivity and system-wide Resource Management on multi-core platforms 209
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 206
On the Role of Context in the Design of Mobile Mashups 203
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods 202
Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures 198
A framework for Compiler Level statistical analysis over customized VLIW architecture 198
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems 198
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures 195
Design Space Exploration Supporting Run-time Resource Management 195
Parallel paradigms and run-time management techniques for many-core architectures: the 2parma approach 194
A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization 193
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems 191
An Instruction-Level Energy Model for Embedded VLIW Architectures 188
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications 182
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models 182
Parallel paradigms and run-time management techniques for many-core architectures 181
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures 180
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 180
An Agent-based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems 179
A Power Modeling and Estimation Framework for VLIW-based Embedded Systems 178
Symbolic Analysis of Higher-Order Side Channel Countermeasures 175
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors 172
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration 171
Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips 171
Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models 169
On the spectral features of robust probing security 169
Low-Power Data Forwarding for VLIW Embedded Architectures 164
ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems 163
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip 162
ADD-based Spectral Analysis of Probing Security 160
Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics 159
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach 159
Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems 158
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 158
Conversational Data Exploration 157
Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming 155
MULTICUBE: Multi-objective design space exploration of multi-core architectures 154
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling 153
A power attack methodology to AES based on induced cache misses: procedure, evaluation and possible countermeasures 153
Context-aware access to heterogeneous resources through on-the-fly mashups 153
Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques 152
Instruction-Level Power Estimation for Embedded VLIW Cores 150
Power Exploration for Embedded VLIW Architectures 146
Robust Optimization of SoC Architectures: A Multi-Scenario Approach 144
Energy-Performance Design Space Exploration of SMT Architectures Exploiting Selective Load Value Predictions 140
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture 140
A relation calculus for reasoning about t-probing security 139
Multi-Objective Design Space Exploration of Embedded Systems 137
Darth's Saber: A Key Exfiltration Attack for Symmetric Ciphers Using Laser Light 137
Design-space exploration and runtime resource management for multicores 136
The MULTICUBE Design Flow 134
An industrial design space exploration framework for supporting run-time resource management on multi-core systems 133
OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces 131
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration 130
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction 130
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures 129
CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks 126
Power-Performance System-Level Exploration of a MicroSPARC2-based Embedded Architecture 124
How might the iPad change healthcare? 124
Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors 122
Optimization Algorithms for Design Space Exploration of Embedded Systems 122
Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors 121
Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration 117
Efficient Attack-Surface Exploration for Electromagnetic Fault Injection 115
Reducing the complexity of instruction-level power models for VLIW processors 115
ConceptOS: A Micro-Kernel Approach to Firmware Updates of Always-On Resource-Constrained Hubris-Based IoT Systems 114
Design Space Exploration of Parallel Architectures 113
An F-algebra for analysing information leaks in the presence of glitches 112
Spectral Features of Higher-Order Side-Channel Countermeasures 111
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip 108
Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product 108
Power Reduction on VLIW Processors through Data Forwarding 107
Processor architecture with variable-stage pipeline 105
On robust strong-non-interferent low-latency multiplications 105
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 102
Toward truly personal chatbots: On the Development of Custom Conversational Assistants 102
Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework 101
Processor Architecture 98
Response Surface Modeling for Design Space Exploration of Embedded Systems 96
Layer-wise Exploration of a Neural Processing Unit Compiler's Optimization Space 92
An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks 88
Low Effort, High Accuracy Network-on-Chip Power Macro ModelingIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 76
Totale 16.266
Salva come PNG Salva come JPEG
Categoria #
all - tutte 46.355
article - articoli 11.021
book - libri 399
conference - conferenze 29.881
curatela - curatele 0
other - altro 0
patent - brevetti 890
selected - selezionate 0
volume - volumi 3.858
Totale 92.404
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/2022863 30 151 64 34 111 49 50 53 38 43 88 152
2022/2023945 120 81 19 132 105 125 7 68 144 65 60 19
2023/2024424 32 91 27 39 40 46 19 32 0 21 5 72
2024/20251.699 14 57 49 28 276 110 63 181 224 128 281 288
2025/20266.596 1.081 1.095 295 489 358 381 1.088 312 343 619 128 407
2026/202776 76 0 0 0 0 0 0 0 0 0 0 0
Totale 16.385