RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ZACCARIA, VITTORIO
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
NA - Nord America 6.322
EU - Europa 1.536
AS - Asia 586
AF - Africa 13
SA - Sud America 4
Continente sconosciuto - Info sul continente non disponibili 2
OC - Oceania 2
Totale 8.465
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 6.239
IT - Italia 310
UA - Ucraina 271
SE - Svezia 245
SG - Singapore 195
VN - Vietnam 193
DE - Germania 168
FI - Finlandia 125
GB - Regno Unito 112
CN - Cina 101
AT - Austria 100
CA - Canada 83
IE - Irlanda 66
ES - Italia 51
IN - India 33
JO - Giordania 29
NL - Olanda 27
BE - Belgio 19
FR - Francia 18
ID - Indonesia 12
KR - Corea 7
BJ - Benin 5
CI - Costa d'Avorio 5
BG - Bulgaria 4
CH - Svizzera 3
PL - Polonia 3
RU - Federazione Russa 3
AR - Argentina 2
AU - Australia 2
EU - Europa 2
GR - Grecia 2
HK - Hong Kong 2
IQ - Iraq 2
JP - Giappone 2
MU - Mauritius 2
PK - Pakistan 2
RO - Romania 2
AL - Albania 1
BD - Bangladesh 1
BR - Brasile 1
CL - Cile 1
EE - Estonia 1
HU - Ungheria 1
IL - Israele 1
IR - Iran 1
LB - Libano 1
LK - Sri Lanka 1
LT - Lituania 1
LV - Lettonia 1
NO - Norvegia 1
OM - Oman 1
PH - Filippine 1
PT - Portogallo 1
TR - Turchia 1
ZA - Sudafrica 1
Totale 8.465
Salva come PNG Salva come JPEG
Città #
Fairfield 1.030
Woodbridge 673
Houston 593
Ashburn 513
Seattle 463
Chandler 423
Wilmington 393
Cambridge 386
Ann Arbor 319
Santa Clara 203
Jacksonville 157
Singapore 149
Boardman 135
Dearborn 122
Dong Ket 97
Medford 94
Lawrence 92
Vienna 92
Ottawa 80
Dublin 66
Milan 63
San Diego 57
Málaga 44
Helsinki 40
Beijing 38
Des Moines 37
Amman 29
Amsterdam 20
Brussels 19
New York 18
Auburn Hills 13
Mountain View 13
Shanghai 13
Norwalk 12
Jakarta 11
Columbus 10
Lucca 10
Verona 10
London 9
Dallas 8
Indiana 8
Falls Church 7
Redwood City 7
Abidjan 5
Cotonou 5
Los Angeles 5
Miami 5
Seongnam 5
Washington 5
Falkenstein 4
Kilburn 4
Klagenfurt 4
Kunming 4
Stockholm 4
Chiswick 3
Frankfurt am Main 3
Graz 3
Grenoble 3
Groningen 3
Guangzhou 3
Hefei 3
Kaisheim 3
Livorno 3
Medina 3
Nanjing 3
Prescot 3
Redmond 3
Tappahannock 3
Warsaw 3
Acton 2
Bangalore 2
Barcelona 2
Bergamo 2
Bern 2
Bochum 2
Bologna 2
Cesa 2
College Park 2
Como 2
Edinburgh 2
Florence 2
Greenbelt 2
Jinan 2
Meda 2
Munich 2
Nanchang 2
Nuremberg 2
Pioltello 2
Pontassieve 2
Pordenone 2
Reggio Emilia 2
Rome 2
San Michele Al Tagliamento 2
St Louis 2
Taranto 2
Torre Del Greco 2
Tres Cantos 2
Vigevano 2
Whyteleafe 2
Wuhan 2
Totale 6.733
Salva come PNG Salva come JPEG
Nome #
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis 165
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 152
Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering 146
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures. 145
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods 141
Branch Prediction Techniques for Low-Power VLIW Processors 136
A System-Level Methodology for Fast Multi-Objective Design Space Exploration 135
Design Space Exploration Supporting Run-time Resource Management 133
Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures 132
A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems 130
About the performances of the advanced encryption standard in embedded systems with cache memory 129
AES power attack based on induced cache miss and countermeasure 129
DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling 128
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures 127
A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip 126
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration 119
An instruction-level methodology for power estimation and optimization of embedded VLIW cores 115
A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip 115
A Design Framework to Efficiently Explore Energy-Delay Tradeoffs 114
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors 114
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models 113
On the Role of Context in the Design of Mobile Mashups 112
ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems 110
Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics 109
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip 109
Parallel paradigms and run-time management techniques for many-core architectures: 2parma approach 108
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach 106
Robust Optimization of SoC Architectures: A Multi-Scenario Approach 106
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 104
OpenCL application auto-tuning and run-time resource management for multi-core platforms 104
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 103
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems 102
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 102
Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips 102
An Instruction-Level Energy Model for Embedded VLIW Architectures 100
A framework for Compiler Level statistical analysis over customized VLIW architecture 100
Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming 98
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture 98
Combining application adaptivity and system-wide Resource Management on multi-core platforms 98
Symbolic Analysis of Higher-Order Side Channel Countermeasures 97
A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization 97
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach 95
Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints 95
Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques 93
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures 93
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems 92
Power Exploration for Embedded VLIW Architectures 92
Parallel paradigms and run-time management techniques for many-core architectures 92
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications 92
Instruction-Level Power Estimation for Embedded VLIW Cores 91
Low-Power Data Forwarding for VLIW Embedded Architectures 91
Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems 89
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 88
An Agent-based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems 88
OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces 84
Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models 83
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction 81
Conversational Data Exploration 81
An industrial design space exploration framework for supporting run-time resource management on multi-core systems 79
Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors 79
Multi-Objective Design Space Exploration of Embedded Systems 76
Energy-Performance Design Space Exploration of SMT Architectures Exploiting Selective Load Value Predictions 76
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures 75
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling 74
The MULTICUBE Design Flow 73
How might the iPad change healthcare? 72
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration 70
MULTICUBE: Multi-objective design space exploration of multi-core architectures 70
Power-Performance System-Level Exploration of a MicroSPARC2-based Embedded Architecture 69
A Power Modeling and Estimation Framework for VLIW-based Embedded Systems 67
Design Space Exploration of Parallel Architectures 65
Reducing the complexity of instruction-level power models for VLIW processors 64
Context-aware access to heterogeneous resources through on-the-fly mashups 63
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip 62
Design-space exploration and runtime resource management for multicores 62
On the spectral features of robust probing security 60
Darth's Saber: A Key Exfiltration Attack for Symmetric Ciphers Using Laser Light 59
Optimization Algorithms for Design Space Exploration of Embedded Systems 57
CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks 57
Power Reduction on VLIW Processors through Data Forwarding 55
Spectral Features of Higher-Order Side-Channel Countermeasures 54
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 53
Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration 51
Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework 47
Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors 46
Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product 46
A power attack methodology to AES based on induced cache misses: procedure, evaluation and possible countermeasures 46
An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks 44
Processor architecture with variable-stage pipeline 42
Response Surface Modeling for Design Space Exploration of Embedded Systems 41
An F-algebra for analysing information leaks in the presence of glitches 37
Processor Architecture 36
ADD-based Spectral Analysis of Probing Security 31
Toward truly personal chatbots: On the Development of Custom Conversational Assistants 30
null 29
A relation calculus for reasoning about t-probing security 23
On robust strong-non-interferent low-latency multiplications 22
Low Effort, High Accuracy Network-on-Chip Power Macro ModelingIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17
Efficient Attack-Surface Exploration for Electromagnetic Fault Injection 15
Interruptible Remote Attestation of Low-end IoT Microcontrollers via Performance Counters 9
Totale 8.532
Salva come PNG Salva come JPEG
Categoria #
all - tutte 27.179
article - articoli 6.386
book - libri 231
conference - conferenze 17.666
curatela - curatele 0
other - altro 0
patent - brevetti 432
selected - selezionate 0
volume - volumi 2.317
Totale 54.211
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201.575 0 0 0 0 0 348 306 233 298 105 213 72
2020/20211.314 110 72 126 66 89 93 91 108 87 136 99 237
2021/2022863 30 151 64 34 111 49 50 53 38 43 88 152
2022/2023945 120 81 19 132 105 125 7 68 144 65 60 19
2023/2024424 32 91 27 39 40 46 19 32 0 21 5 72
2024/2025534 14 57 49 28 276 110 0 0 0 0 0 0
Totale 8.548