RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ZACCARIA, VITTORIO
 Distribuzione geografica
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Continente #
NA - Nord America 6.000
EU - Europa 1.483
AS - Asia 353
AF - Africa 7
Continente sconosciuto - Info sul continente non disponibili 2
OC - Oceania 2
SA - Sud America 2
Totale 7.849
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Nazione #
US - Stati Uniti d'America 5.917
IT - Italia 293
UA - Ucraina 269
SE - Svezia 243
VN - Vietnam 193
DE - Germania 159
FI - Finlandia 124
GB - Regno Unito 109
AT - Austria 98
CA - Canada 83
CN - Cina 78
IE - Irlanda 66
ES - Italia 51
IN - India 33
JO - Giordania 29
NL - Olanda 23
BE - Belgio 17
FR - Francia 16
KR - Corea 7
CI - Costa d'Avorio 5
SG - Singapore 4
CH - Svizzera 3
PL - Polonia 3
AU - Australia 2
EU - Europa 2
GR - Grecia 2
ID - Indonesia 2
IQ - Iraq 2
MU - Mauritius 2
RO - Romania 2
AL - Albania 1
AR - Argentina 1
BR - Brasile 1
HK - Hong Kong 1
HU - Ungheria 1
IR - Iran 1
LB - Libano 1
NO - Norvegia 1
OM - Oman 1
PH - Filippine 1
PT - Portogallo 1
RU - Federazione Russa 1
Totale 7.849
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Città #
Fairfield 1.030
Woodbridge 673
Houston 593
Ashburn 511
Seattle 463
Chandler 423
Wilmington 393
Cambridge 386
Ann Arbor 319
Jacksonville 157
Dearborn 122
Dong Ket 97
Medford 94
Lawrence 92
Vienna 91
Ottawa 80
Dublin 66
Milan 62
San Diego 57
Málaga 44
Helsinki 39
Beijing 38
Des Moines 37
Boardman 31
Amman 29
Amsterdam 17
Brussels 17
New York 16
Auburn Hills 13
Mountain View 13
Norwalk 12
Shanghai 11
Columbus 10
Lucca 10
Verona 10
Dallas 8
Indiana 8
Falls Church 7
London 7
Redwood City 7
Abidjan 5
Miami 5
Seongnam 5
Washington 5
Kilburn 4
Klagenfurt 4
Kunming 4
Chiswick 3
Falkenstein 3
Graz 3
Grenoble 3
Groningen 3
Hefei 3
Kaisheim 3
Livorno 3
Los Angeles 3
Medina 3
Prescot 3
Redmond 3
Tappahannock 3
Warsaw 3
Acton 2
Bangalore 2
Barcelona 2
Bergamo 2
Bern 2
Bochum 2
College Park 2
Como 2
Edinburgh 2
Florence 2
Greenbelt 2
Guangzhou 2
Jinan 2
Meda 2
Nanchang 2
Nanjing 2
Pioltello 2
Pontassieve 2
Pordenone 2
Reggio Emilia 2
Rome 2
San Michele Al Tagliamento 2
St Louis 2
Stockholm 2
Taranto 2
Torre Del Greco 2
Tres Cantos 2
Vigevano 2
Whyteleafe 2
Wuhan 2
Aachen 1
Abbiategrasso 1
Agropoli 1
Atlanta 1
Berlin 1
Boston 1
Breda di Piave 1
Budapest 1
Cattolica 1
Totale 6.236
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Nome #
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis 158
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 147
Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering 139
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures. 137
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods 135
A System-Level Methodology for Fast Multi-Objective Design Space Exploration 132
Branch Prediction Techniques for Low-Power VLIW Processors 130
Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures 128
Design Space Exploration Supporting Run-time Resource Management 127
A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems 125
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures 123
DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling 122
A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip 120
AES power attack based on induced cache miss and countermeasure 119
About the performances of the advanced encryption standard in embedded systems with cache memory 116
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration 116
An instruction-level methodology for power estimation and optimization of embedded VLIW cores 111
A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip 111
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models 111
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors 108
Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics 106
A Design Framework to Efficiently Explore Energy-Delay Tradeoffs 106
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip 106
ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems 103
Robust Optimization of SoC Architectures: A Multi-Scenario Approach 103
Parallel paradigms and run-time management techniques for many-core architectures: 2parma approach 100
On the Role of Context in the Design of Mobile Mashups 100
Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips 99
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 98
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach 98
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems 96
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 95
An Instruction-Level Energy Model for Embedded VLIW Architectures 94
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture 94
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 93
Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming 93
Symbolic Analysis of Higher-Order Side Channel Countermeasures 93
OpenCL application auto-tuning and run-time resource management for multi-core platforms 93
A framework for Compiler Level statistical analysis over customized VLIW architecture 92
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach 91
A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization 91
Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques 90
Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints 90
Combining application adaptivity and system-wide Resource Management on multi-core platforms 89
Power Exploration for Embedded VLIW Architectures 88
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 86
Instruction-Level Power Estimation for Embedded VLIW Cores 85
Low-Power Data Forwarding for VLIW Embedded Architectures 85
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems 85
Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems 84
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications 84
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures 84
Parallel paradigms and run-time management techniques for many-core architectures 83
OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces 81
An Agent-based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems 79
Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models 78
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction 76
An industrial design space exploration framework for supporting run-time resource management on multi-core systems 74
Conversational Data Exploration 74
Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors 74
Energy-Performance Design Space Exploration of SMT Architectures Exploiting Selective Load Value Predictions 73
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures 73
Multi-Objective Design Space Exploration of Embedded Systems 71
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling 69
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration 67
How might the iPad change healthcare? 67
The MULTICUBE Design Flow 66
MULTICUBE: Multi-objective design space exploration of multi-core architectures 66
Power-Performance System-Level Exploration of a MicroSPARC2-based Embedded Architecture 65
A Power Modeling and Estimation Framework for VLIW-based Embedded Systems 61
Reducing the complexity of instruction-level power models for VLIW processors 59
Design Space Exploration of Parallel Architectures 58
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip 58
Context-aware access to heterogeneous resources through on-the-fly mashups 57
Design-space exploration and runtime resource management for multicores 56
Optimization Algorithms for Design Space Exploration of Embedded Systems 53
Darth's Saber: A Key Exfiltration Attack for Symmetric Ciphers Using Laser Light 52
CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks 50
Power Reduction on VLIW Processors through Data Forwarding 49
Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration 48
Spectral Features of Higher-Order Side-Channel Countermeasures 48
On the spectral features of robust probing security 48
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 47
Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework 43
Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors 42
Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product 41
Processor architecture with variable-stage pipeline 35
A power attack methodology to AES based on induced cache misses: procedure, evaluation and possible countermeasures 34
Response Surface Modeling for Design Space Exploration of Embedded Systems 33
An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks 32
An F-algebra for analysing information leaks in the presence of glitches 32
Processor Architecture 30
null 29
ADD-based Spectral Analysis of Probing Security 22
Toward truly personal chatbots: On the Development of Custom Conversational Assistants 22
On robust strong-non-interferent low-latency multiplications 15
Low Effort, High Accuracy Network-on-Chip Power Macro ModelingIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 14
A relation calculus for reasoning about t-probing security 13
Efficient Attack-Surface Exploration for Electromagnetic Fault Injection 2
Interruptible Remote Attestation of Low-end IoT Microcontrollers via Performance Counters 1
Totale 7.929
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Categoria #
all - tutte 22.032
article - articoli 5.149
book - libri 190
conference - conferenze 14.422
curatela - curatele 0
other - altro 0
patent - brevetti 305
selected - selezionate 0
volume - volumi 1.856
Totale 43.954
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/2019906 0 0 0 0 0 0 0 0 0 196 386 324
2019/20202.414 147 128 48 201 315 348 306 233 298 105 213 72
2020/20211.314 110 72 126 66 89 93 91 108 87 136 99 237
2021/2022863 30 151 64 34 111 49 50 53 38 43 88 152
2022/2023945 120 81 19 132 105 125 7 68 144 65 60 19
2023/2024339 32 91 27 39 40 46 19 32 0 13 0 0
Totale 7.929