RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ZACCARIA, VITTORIO
 Distribuzione geografica
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Continente #
NA - Nord America 7.340
EU - Europa 3.179
AS - Asia 1.900
SA - Sud America 551
AF - Africa 72
OC - Oceania 4
Continente sconosciuto - Info sul continente non disponibili 2
Totale 13.048
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Nazione #
US - Stati Uniti d'America 7.219
RU - Federazione Russa 1.382
SG - Singapore 740
CN - Cina 571
BR - Brasile 475
IT - Italia 330
UA - Ucraina 280
VN - Vietnam 265
SE - Svezia 256
DE - Germania 205
GB - Regno Unito 151
FI - Finlandia 141
AT - Austria 103
CA - Canada 99
IE - Irlanda 67
FR - Francia 65
ES - Italia 60
IN - India 60
NL - Olanda 60
KR - Corea 50
HK - Hong Kong 33
JO - Giordania 33
AR - Argentina 29
BD - Bangladesh 28
MA - Marocco 27
EC - Ecuador 20
ID - Indonesia 20
BE - Belgio 19
PL - Polonia 19
ZA - Sudafrica 18
IQ - Iraq 14
JP - Giappone 14
VE - Venezuela 13
MX - Messico 12
TR - Turchia 11
PK - Pakistan 9
PY - Paraguay 8
CI - Costa d'Avorio 7
SA - Arabia Saudita 7
UZ - Uzbekistan 7
AE - Emirati Arabi Uniti 5
AZ - Azerbaigian 5
BG - Bulgaria 5
BJ - Benin 5
KE - Kenya 5
LT - Lituania 5
RO - Romania 5
AU - Australia 4
CH - Svizzera 4
OM - Oman 4
BH - Bahrain 3
CZ - Repubblica Ceca 3
EG - Egitto 3
IL - Israele 3
IR - Iran 3
LB - Libano 3
NP - Nepal 3
PT - Portogallo 3
AL - Albania 2
BO - Bolivia 2
CR - Costa Rica 2
DO - Repubblica Dominicana 2
EU - Europa 2
GR - Grecia 2
KG - Kirghizistan 2
MU - Mauritius 2
PE - Perù 2
PH - Filippine 2
SN - Senegal 2
AD - Andorra 1
BB - Barbados 1
BS - Bahamas 1
BY - Bielorussia 1
CL - Cile 1
CO - Colombia 1
DZ - Algeria 1
EE - Estonia 1
ET - Etiopia 1
GI - Gibilterra 1
GT - Guatemala 1
HU - Ungheria 1
LK - Sri Lanka 1
LV - Lettonia 1
MD - Moldavia 1
ME - Montenegro 1
MK - Macedonia 1
NI - Nicaragua 1
NO - Norvegia 1
PA - Panama 1
PS - Palestinian Territory 1
RS - Serbia 1
SK - Slovacchia (Repubblica Slovacca) 1
TH - Thailandia 1
TM - Turkmenistan 1
TN - Tunisia 1
TT - Trinidad e Tobago 1
TW - Taiwan 1
Totale 13.048
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Città #
Fairfield 1.030
Ashburn 891
Woodbridge 673
Houston 597
Seattle 463
Singapore 436
Chandler 423
Wilmington 393
Cambridge 386
Ann Arbor 319
Santa Clara 207
Moscow 205
Beijing 174
Jacksonville 157
Boardman 135
Hefei 129
Dearborn 122
Council Bluffs 98
Dong Ket 97
Medford 94
Lawrence 92
Vienna 92
Ottawa 80
Dublin 67
Milan 66
Los Angeles 60
San Diego 58
Dallas 55
São Paulo 48
Málaga 44
Seoul 43
Helsinki 40
Des Moines 38
Buffalo 34
Amman 33
New York 32
The Dalles 32
Casablanca 26
Hong Kong 25
Amsterdam 24
London 23
Hanoi 22
Brussels 19
Ho Chi Minh City 17
Rio de Janeiro 16
Shanghai 16
Stockholm 15
Frankfurt am Main 14
Turku 14
Auburn Hills 13
Brooklyn 13
Chicago 13
Mountain View 13
Belo Horizonte 12
Kent 12
Norwalk 12
Orem 12
Warsaw 12
Columbus 11
Jakarta 11
Nuremberg 11
Lucca 10
Montreal 10
Redondo Beach 10
Tokyo 10
Verona 10
Curitiba 9
Denver 9
Guangzhou 9
Johannesburg 9
Düsseldorf 8
Indiana 8
Poplar 8
Abidjan 7
Falls Church 7
Guayaquil 7
Lauterbourg 7
Munich 7
Redwood City 7
Washington 7
Aracaju 6
Brasília 6
Dhaka 6
Elk Grove Village 6
Ha Kwai Chung 6
Miami 6
Phoenix 6
Salvador 6
Tashkent 6
Tianjin 6
Turin 6
Baku 5
Buenos Aires 5
Chennai 5
Cotonou 5
Erbil 5
Juiz de Fora 5
Manchester 5
Porto Alegre 5
Santo André 5
Totale 8.589
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Nome #
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures. 221
AES power attack based on induced cache miss and countermeasure 210
A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems 206
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis 204
A Design Framework to Efficiently Explore Energy-Delay Tradeoffs 204
About the performances of the advanced encryption standard in embedded systems with cache memory 200
Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering 194
A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip 193
A System-Level Methodology for Fast Multi-Objective Design Space Exploration 186
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 185
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 185
An instruction-level methodology for power estimation and optimization of embedded VLIW cores 184
DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling 184
Branch Prediction Techniques for Low-Power VLIW Processors 183
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach 177
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods 176
A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip 175
OpenCL application auto-tuning and run-time resource management for multi-core platforms 172
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 170
Design Space Exploration Supporting Run-time Resource Management 168
Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints 168
Parallel paradigms and run-time management techniques for many-core architectures: the 2parma approach 164
A framework for Compiler Level statistical analysis over customized VLIW architecture 163
On the Role of Context in the Design of Mobile Mashups 163
Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures 161
A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization 159
Combining application adaptivity and system-wide Resource Management on multi-core platforms 159
An Instruction-Level Energy Model for Embedded VLIW Architectures 156
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures 156
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications 155
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors 153
Parallel paradigms and run-time management techniques for many-core architectures 152
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems 151
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems 151
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration 150
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models 150
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures 149
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 147
Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips 145
Improving Simulation Speed and Accuracy for Many-Core Embedded Platforms with Ensemble Models 144
Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics 143
An Agent-based Approach to Full Interoperability and Allocation Transparency in Distributed File Systems 142
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip 141
ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems 137
A Power Modeling and Estimation Framework for VLIW-based Embedded Systems 133
Low-Power Data Forwarding for VLIW Embedded Architectures 132
Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems 131
Symbolic Analysis of Higher-Order Side Channel Countermeasures 131
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 130
Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming 128
Power Exploration for Embedded VLIW Architectures 128
MULTICUBE: Multi-objective design space exploration of multi-core architectures 128
Instruction-Level Power Estimation for Embedded VLIW Cores 127
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach 126
On the spectral features of robust probing security 126
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling 125
Robust Optimization of SoC Architectures: A Multi-Scenario Approach 125
Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques 124
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture 123
Conversational Data Exploration 117
ADD-based Spectral Analysis of Probing Security 112
A power attack methodology to AES based on induced cache misses: procedure, evaluation and possible countermeasures 111
Context-aware access to heterogeneous resources through on-the-fly mashups 109
Energy-Performance Design Space Exploration of SMT Architectures Exploiting Selective Load Value Predictions 108
CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks 107
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction 106
An industrial design space exploration framework for supporting run-time resource management on multi-core systems 105
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures 105
OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces 105
Darth's Saber: A Key Exfiltration Attack for Symmetric Ciphers Using Laser Light 105
The MULTICUBE Design Flow 103
Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors 103
Multi-Objective Design Space Exploration of Embedded Systems 101
Power-Performance System-Level Exploration of a MicroSPARC2-based Embedded Architecture 100
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration 100
How might the iPad change healthcare? 99
Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors 98
A relation calculus for reasoning about t-probing security 97
Design-space exploration and runtime resource management for multicores 97
Design Space Exploration of Parallel Architectures 93
Optimization Algorithms for Design Space Exploration of Embedded Systems 93
Reducing the complexity of instruction-level power models for VLIW processors 91
Power Reduction on VLIW Processors through Data Forwarding 90
Spectral Features of Higher-Order Side-Channel Countermeasures 90
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip 83
Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration 82
Efficient Attack-Surface Exploration for Electromagnetic Fault Injection 78
On robust strong-non-interferent low-latency multiplications 78
An F-algebra for analysing information leaks in the presence of glitches 77
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 76
Processor architecture with variable-stage pipeline 75
Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product 74
ConceptOS: A Micro-Kernel Approach to Firmware Updates of Always-On Resource-Constrained Hubris-Based IoT Systems 73
Response Surface Modeling for Design Space Exploration of Embedded Systems 73
An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks 71
Processor Architecture 69
Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework 69
Layer-wise Exploration of a Neural Processing Unit Compiler's Optimization Space 63
Toward truly personal chatbots: On the Development of Custom Conversational Assistants 61
Low Effort, High Accuracy Network-on-Chip Power Macro ModelingIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 55
Totale 13.055
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Categoria #
all - tutte 39.419
article - articoli 9.313
book - libri 335
conference - conferenze 25.545
curatela - curatele 0
other - altro 0
patent - brevetti 699
selected - selezionate 0
volume - volumi 3.286
Totale 78.597
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021851 0 0 0 0 0 93 91 108 87 136 99 237
2021/2022863 30 151 64 34 111 49 50 53 38 43 88 152
2022/2023945 120 81 19 132 105 125 7 68 144 65 60 19
2023/2024424 32 91 27 39 40 46 19 32 0 21 5 72
2024/20251.699 14 57 49 28 276 110 63 181 224 128 281 288
2025/20263.418 1.081 1.095 295 489 358 100 0 0 0 0 0 0
Totale 13.131