This paper describes the architectural exploration of the system-level parameters for a MicroSPARC2-based embedded system. The overall goal of the exploration task is to quickly identify the best architecture of the embedded system in terms of both energy and delay parameters, avoiding the comprehensive analysis of the architectural design space. The Energy-Delay Product (EDP) has been adopted as the evaluation metric to compare the alternative architectures in terms of different cache memory and bus subsystems. The exploration phase adopts an iterative local-search algorithm based on the sensitivity analysis of the cost function with respect to the tuning parameters of system architecture. The exploration targets the architectural optimisation of the parameters related to the cache memory and the bus sub-systems of an embedded architecture based on the MicroSPARC2 architecture executing the set of Mediabench benchmarks for multimedia applications. The experimental results ha ve shown a reduction up to nine orders of magnitude ofthe n umber of design alternatives analyzed during the exploration phase.

Power-Performance System-Level Exploration of a MicroSPARC2-based Embedded Architecture

PALERMO, GIANLUCA;SILVANO, CRISTINA;ZACCARIA, VITTORIO
2003

Abstract

This paper describes the architectural exploration of the system-level parameters for a MicroSPARC2-based embedded system. The overall goal of the exploration task is to quickly identify the best architecture of the embedded system in terms of both energy and delay parameters, avoiding the comprehensive analysis of the architectural design space. The Energy-Delay Product (EDP) has been adopted as the evaluation metric to compare the alternative architectures in terms of different cache memory and bus subsystems. The exploration phase adopts an iterative local-search algorithm based on the sensitivity analysis of the cost function with respect to the tuning parameters of system architecture. The exploration targets the architectural optimisation of the parameters related to the cache memory and the bus sub-systems of an embedded architecture based on the MicroSPARC2 architecture executing the set of Mediabench benchmarks for multimedia applications. The experimental results ha ve shown a reduction up to nine orders of magnitude ofthe n umber of design alternatives analyzed during the exploration phase.
Proceedings of DATE 2003 Designers Forum: IEEE Design, Automation and Test Conference
0769518702
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/271783
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