Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip

Application-specific network-centric architectures (such as Networks on-Chip, NoCs) have recently become an effective solution to sup- port high bandwidth communication in Multiprocessor Systems- on-Chip (MPSoCs). Moreover, the introduction of the hierarchy concept in the NoC design benefits from the main locality nature of the communication in MPSoC architectures. This paper presents a methodology to design Application Specific Hierarchical NoC (ASHiNoC) architectures considering foorplanning information. The presented approach targets heterogeneous clustered architectures where the intra-cluster communication is managed by a low-latency circuit-switched crossbar, while the inter-cluster communications are managed by a high-bandwidth packet-based NoC, allowing reg- ulars topologies. The proposed design flow faces the problem by starting from the cluster selection down-to the foorplanning-aware estimation of the interconnect performances in terms of latency, power, area within each cluster and for the backbone NoC. Exper- imental results show that the AHiNoC architecture is able to guar- antee an interconnection power and latency reduction of 49% and 33% respectively, at a cost of an area increment of 78% with respect to a flat topology version.