PALERMO, GIANLUCA
 Distribuzione geografica
Continente #
NA - Nord America 11.795
EU - Europa 2.977
AS - Asia 1.063
AF - Africa 32
SA - Sud America 22
OC - Oceania 6
Continente sconosciuto - Info sul continente non disponibili 5
Totale 15.900
Nazione #
US - Stati Uniti d'America 11.641
IT - Italia 888
UA - Ucraina 404
VN - Vietnam 356
SE - Svezia 337
SG - Singapore 308
DE - Germania 270
FI - Finlandia 237
CN - Cina 206
AT - Austria 205
GB - Regno Unito 171
ES - Italia 156
CA - Canada 152
IE - Irlanda 119
IN - India 54
ID - Indonesia 49
NL - Olanda 43
BE - Belgio 42
FR - Francia 40
JO - Giordania 32
BR - Brasile 17
HK - Hong Kong 15
CI - Costa d'Avorio 12
CZ - Repubblica Ceca 11
GR - Grecia 11
CH - Svizzera 10
JP - Giappone 10
BJ - Benin 9
KR - Corea 9
RU - Federazione Russa 9
MU - Mauritius 8
PL - Polonia 8
TR - Turchia 7
EU - Europa 5
AL - Albania 4
PH - Filippine 4
PK - Pakistan 4
PT - Portogallo 4
AU - Australia 3
NO - Norvegia 3
NZ - Nuova Zelanda 3
AR - Argentina 2
IQ - Iraq 2
AE - Emirati Arabi Uniti 1
AM - Armenia 1
AZ - Azerbaigian 1
BO - Bolivia 1
DO - Repubblica Dominicana 1
DZ - Algeria 1
EC - Ecuador 1
EE - Estonia 1
HU - Ungheria 1
IL - Israele 1
IR - Iran 1
LT - Lituania 1
LV - Lettonia 1
MA - Marocco 1
OM - Oman 1
PA - Panama 1
PY - Paraguay 1
RO - Romania 1
TH - Thailandia 1
ZA - Sudafrica 1
Totale 15.900
Città #
Fairfield 1.961
Woodbridge 1.250
Ashburn 1.018
Houston 966
Seattle 837
Chandler 814
Wilmington 752
Cambridge 741
Ann Arbor 607
Santa Clara 372
Milan 308
Boardman 247
Jacksonville 232
Dearborn 218
Vienna 204
Dong Ket 199
Singapore 196
Medford 163
Lawrence 156
Málaga 148
Ottawa 142
Dublin 115
Helsinki 89
San Diego 82
Beijing 66
Des Moines 58
Jakarta 49
Norwalk 43
Brussels 36
Redwood City 33
Amman 32
Rome 30
Amsterdam 28
New York 27
Shanghai 25
Mountain View 23
Falls Church 22
Indiana 21
Auburn Hills 18
Florence 18
London 18
Miami 17
Los Angeles 13
Verona 13
Abidjan 12
Redmond 12
Hong Kong 11
Phoenix 11
Frankfurt am Main 10
Bologna 9
Columbus 9
Cotonou 9
Lappeenranta 9
Washington 9
Bergamo 8
Groningen 8
Richland 8
The Dalles 8
Yellow Springs 8
Hefei 7
Turin 7
Guangzhou 6
Kunming 6
Munich 6
Nanjing 6
Seongnam 6
Warsaw 6
Berlin 5
Falkenstein 5
Muglinov 5
Seregno 5
Siena 5
Tokyo 5
Vedano al Lambro 5
Bresso 4
Chiswick 4
Fremont 4
Gavirate 4
Kilburn 4
Livorno 4
Manila 4
Nanchang 4
Nuremberg 4
Americana 3
Athens 3
Atlanta 3
Bern 3
Cortenuova 3
Enna 3
Erbusco 3
Forest City 3
Gelsenkirchen 3
Grenoble 3
Izmir 3
Jinan 3
Kumar 3
Limbiate 3
Lisbon 3
Madrid 3
Napoli 3
Totale 12.720
Nome #
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level 196
A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA 180
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties 172
An Evolutionary Approach to Area-Time Optimization of FPGA designs 166
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis 165
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors 163
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 152
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures. 145
The Combined Perceptron Branch Predictor 142
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip 141
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods 141
Efficiency and Scalability of Barrier Synchronization on NoC Based Many-core Architectures 140
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 140
Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs 139
A multiprocessor self-reconfigurable jpeg2000 encoder 139
Low-power Architectures for Mobile Systems 137
Throughput balancing for energy efficient near-threshold manycores 137
Accelerating a Geometric Approach to Molecular Docking with OpenACC 137
Branch Prediction Techniques for Low-Power VLIW Processors 136
A Data Protection Unit for NoC-based Architectures 136
The ANTAREX approach to autotuning and adaptivity for energy efficient HPC Systems 136
Real-time considerations for rugged embedded systems 136
A System-Level Methodology for Fast Multi-Objective Design Space Exploration 135
Exploring efficient hardware support for applications with irregular memory patterns on multinode manycore architectures 135
Design Space Exploration Supporting Run-time Resource Management 133
Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures 132
A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems 130
AES power attack based on induced cache miss and countermeasure 129
DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling 128
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs 127
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures 127
A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip 126
An Efficient Synchronization Technique for Multiprocessor Systems on-Chip 124
Application autotuning to support runtime adaptivity in multicore architectures 124
mARGOt: a Dynamic Autotuning Framework for Self-aware Approximate Computing 123
Lightweight DMA management mechanisms for multiprocessors on FPGA 122
A Compact Transactional Memory Multiprocessor System on FPGA 121
Mapping and Topology Customization Approaches for Application-Specific STNoC Designs 120
CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties 120
SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications 119
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration 119
A Security Monitoring Service for NoCs 117
Automatic parallelization of sequential specifications for symmetric MPSoCs 116
Early stage interference checking for automatic design space exploration of mixed critical systems 116
MiCOMP: Mitigating the Compiler Phase-Ordering Problem Using Optimization Sub-Sequences and Machine Learning 116
Self Reconfigurable Implementation of the JPEG Encoder 115
A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip 115
A Topology Design Customization Approach for STNoC 114
ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models 113
An Interrupt Controller for FPGA-based Multiprocessors 112
ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems 110
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip 109
Parallel paradigms and run-time management techniques for many-core architectures: 2parma approach 108
A survey on compiler autotuning using machine learning 107
Run-time resource management based on design space exploration 107
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach 106
Robust Optimization of SoC Architectures: A Multi-Scenario Approach 106
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 104
COBAYN: Compiler autotuning framework using Bayesian networks 104
A dual-priority real-time multiprocessor system on FPGA for automotive applications 104
OpenCL application auto-tuning and run-time resource management for multi-core platforms 104
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures 103
Floorplan-aware hierarchical NoC topology with GALS interfaces 102
Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips 102
ANTAREX - AutoTuning and adaptivity approach for energy efficient eXascale HPC systems 102
Energy/Performance Evaluation of the Multithreaded Extion of a Muulticluster VLIW Processor 100
A framework for Compiler Level statistical analysis over customized VLIW architecture 100
A system-level exploration of power delivery architectures for near-threshold manycores considering performance constraints 99
An Efficient Monte Carlo-based Probabilistic Time-Dependent Routing Calculation Targeting a Server-Side Car Navigation System 99
The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems 99
Design Space Exploration for Run-time Management of a Reconfigurable System for Video Streaming 98
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture 98
Combining application adaptivity and system-wide Resource Management on multi-core platforms 98
Predictive modeling methodology for compiler phase-ordering 97
A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization 97
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach 95
Customization of OpenCL Applications for Efficient Task Mapping Under Heterogeneous Platform Constraints 95
The ANTAREX domain specific language for high performance computing 94
Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques 93
Efficient Architecture/Compiler Co-Exploration Using Analytical Models 93
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures 93
Guest Editorial: Special Issue on Computing Frontiers 93
A Monitoring System for NoCs 92
Parallel paradigms and run-time management techniques for many-core architectures 92
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications 92
PIRATE: A Framework for Power/Performance Exploration of Network-On-Chip Architectures 92
Exploiting OpenMP and OpenACC to accelerate a geometric approach to molecular docking in heterogeneous HPC nodes 92
Multi-Objective Co-Exploration of Source Code Transformations and Design Space Architecture for Low-Power Embedded Systems 91
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors 91
A Bayesian network approach for compiler auto-tuning for embedded processors 91
Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs 91
The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems 90
Variability-Aware Voltage Island Management for Near-Threshold Computing with Performance Guarantees 89
A reconfigurable multiprocessor architecture for a reliable face recognition implementation 87
COMPLEX - COdesign and power Management in PLatform-based design space EXploration 87
Computer implemented method for determining an optimal positional matching of a binding molecule in a docking site of a target molecule 86
Implementation of a Reconfigurable Data Protection Module for NoC-based MPSoC 85
Prototyping pipelined applications on a heterogeneous fpga multiprocessor virtual platform 85
Application-Specific Topology Design Customization for STNoC 84
OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Spaces 84
Totale 11.524
Categoria #
all - tutte 52.017
article - articoli 12.022
book - libri 279
conference - conferenze 35.913
curatela - curatele 385
other - altro 0
patent - brevetti 359
selected - selezionate 0
volume - volumi 3.059
Totale 104.034


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20202.302 0 0 0 0 0 0 582 440 548 215 374 143
2020/20212.352 191 153 205 124 159 110 168 219 159 274 174 416
2021/20221.586 92 223 135 67 189 97 85 117 70 89 158 264
2022/20231.910 217 124 71 252 197 264 7 134 282 208 111 43
2023/20241.060 75 163 65 88 80 124 47 95 14 78 77 154
2024/20251.033 9 58 128 68 516 253 1 0 0 0 0 0
Totale 16.110