FORNACIARI, WILLIAM

FORNACIARI, WILLIAM  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Titolo Data di pubblicazione Autori File
3D-ICE 3.0: efficient nonlinear MPSoC thermal simulation with pluggable heat sink models 1-gen-2021 Terraneo, FedericoLeva, AlbertoFornaciari, William +
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 1-gen-2002 FORNACIARI, WILLIAMSCIUTO, DONATELLASILVANO, CRISTINAZACCARIA, VITTORIO
Affinity-driven system design exploration for heterogeneous multiprocessor SoC 1-gen-2006 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA +
All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores 1-gen-2020 Zoni, DavideCremona, LucaFornaciari, William
All-digital energy-constrained controller for general-purpose accelerators and CPUs 1-gen-2019 Davide ZoniLuca CremonaWilliam Fornaciari
APES - Implementation of a CAD tool for array processor design: Textual definition versus graphic description 1-gen-1990 F. DistantePIURI, VINCENZOFORNACIARI, WILLIAM +
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems 1-gen-2021 Luca CremonaWilliam FornaciariDavide Zoni
BarMan: a Run-Time Management Framework in the Resource Continuum 1-gen-2022 Michele ZanellaFilippo SciamannaWilliam Fornaciari
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers 1-gen-2017 Zoni, DavideCanidio, AndreaFornaciari, William +
A Case Study in Design Space Exploration: The TOSCA Environment Applied to a Telecom Link Controller 1-gen-2000 ALLARA, ALBERTOFORNACIARI, WILLIAMSALICE, FABIO +
chronovise: Measurement-Based Probabilistic Timing Analysis framework 1-gen-2018 F. ReghenzaniG. MassariW. Fornaciari
Co-scheduling tasks on multi-core heterogeneous systems: An energy-aware perspective 1-gen-2016 LIBUTTI, SIMONEMASSARI, GIUSEPPEFORNACIARI, WILLIAM
Co-Synthesis and Co-simulation of Control-Dominated Embedded Systems 1-gen-1996 FORNACIARI, WILLIAMSCIUTO, DONATELLA +
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture 1-gen-2018 D. ZoniA. BarenghiG. PelosiW. Fornaciari
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties 1-gen-2017 PALERMO, GIANLUCAFORNACIARI, WILLIAMBRANDOLESE, CARLOGADIOLI, DAVIDEVITALI, EMANUELEZONI, DAVIDE +
A Control-based Methodology for Power-performance Optimization in NoCs Exploiting DVFS 1-gen-2015 Zoni, DavideTerraneo, FedericoFornaciari, William
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-based NoCs 1-gen-2015 Zoni, DavideFornaciari, William +
DarkCache: Energy-performance Optimization of Tiled Multi-cores by Adaptively Power Gating LLC Banks 1-gen-2018 Davide ZoniWilliam Fornaciari +
Dealing with uncertainty in pWCET estimations 1-gen-2020 Federico ReghenzaniWilliam Fornaciari +
Design of side-channel resistant power monitors 1-gen-2022 Zoni, DavideCremona, LucaFornaciari, William