FORNACIARI, WILLIAM

FORNACIARI, WILLIAM  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Titolo Data di pubblicazione Autori File
3D-ICE 3.0: efficient nonlinear MPSoC thermal simulation with pluggable heat sink models 1-gen-2021 Terraneo, FedericoLeva, AlbertoFornaciari, William +
A Case Study in Design Space Exploration: The TOSCA Environment Applied to a Telecom Link Controller 1-gen-2000 ALLARA, ALBERTOFORNACIARI, WILLIAMSALICE, FABIO +
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture 1-gen-2018 D. ZoniA. BarenghiG. PelosiW. Fornaciari
A Control-based Methodology for Power-performance Optimization in NoCs Exploiting DVFS 1-gen-2015 Zoni, DavideTerraneo, FedericoFornaciari, William
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations 1-gen-2016 ZONI, DAVIDETERRANEO, FEDERICOFORNACIARI, WILLIAM
A new architecture for the automatic design of custom digital neural network 1-gen-1995 FORNACIARI, WILLIAMSALICE, FABIO
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems 1-gen-2002 FORNACIARI, WILLIAMSCIUTO, DONATELLASILVANO, CRISTINAZACCARIA, VITTORIO
A SPICE-Based Approach to Steady-State Circuits Analysis 1-gen-1993 D'AMORE, DARIOFORNACIARI, WILLIAM
A survey on run-time power monitors at the edge 1-gen-2023 Davide ZoniAndrea GalimbertiWilliam Fornaciari
A two-level cosimulation environment 1-gen-1997 FORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
A VHDL-based Approach for Power Estimation of Embedded Systems 1-gen-1997 FORNACIARI, WILLIAMSCIUTO, DONATELLASILVANO, CRISTINA +
Affinity-driven system design exploration for heterogeneous multiprocessor SoC 1-gen-2006 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA +
All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores 1-gen-2020 Zoni, DavideCremona, LucaFornaciari, William
All-digital energy-constrained controller for general-purpose accelerators and CPUs 1-gen-2019 Davide ZoniLuca CremonaWilliam Fornaciari
An FPU design template to optimize the accuracy-efficiency-area trade-off 1-gen-2021 Davide ZoniAndrea GalimbertiWilliam Fornaciari
APES - Implementation of a CAD tool for array processor design: Textual definition versus graphic description 1-gen-1990 F. DistantePIURI, VINCENZOFORNACIARI, WILLIAM +
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems 1-gen-2021 Luca CremonaWilliam FornaciariDavide Zoni
BarMan: a Run-Time Management Framework in the Resource Continuum 1-gen-2022 Michele ZanellaFilippo SciamannaWilliam Fornaciari
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers 1-gen-2017 Zoni, DavideCanidio, AndreaFornaciari, William +
chronovise: Measurement-Based Probabilistic Timing Analysis framework 1-gen-2018 F. ReghenzaniG. MassariW. Fornaciari