RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

DISTANTE, FAUSTO

DISTANTE, FAUSTO  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Titolo Data di pubblicazione Autori File
A Compact and Fast Silicon Implementation for Layered Neural Nets 1-gen-1990 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTORTI GAJANI, GIANCARLO +
A configurable array architecture for WSI implementation of neural nets 1-gen-1990 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTORTI GAJANI, GIANCARLO +
A digital Architecture for Neural Networks 1-gen-1993 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTEFANELLI, RENATOSTORTI GAJANI, GIANCARLO
A general configurable architecture for WSI implementation for neural nets 1-gen-1990 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTORTI GAJANI, GIANCARLO
A Proposal for Neural Macrocell Array 1-gen-1990 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTORTI GAJANI, GIANCARLO +
A semi-custom approach for digital implementation of neural networks 1-gen-1991 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTORTI GAJANI, GIANCARLO +
Alternative Approaches for Mapping Neural Networks onto Silicon 1-gen-1989 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTEFANELLI, RENATOSTORTI GAJANI, GIANCARLO
An Approach for Digital Neural Network Design 1-gen-1991 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTEFANELLI, RENATOSTORTI GAJANI, GIANCARLO
An Array Architecture for WSI Implementation of Neural Nets 1-gen-1990 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTEFANELLI, RENATOSTORTI GAJANI, GIANCARLO
APES - Implementation of a CAD tool for array processor design: Textual definition versus graphic description 1-gen-1990 F. DistantePIURI, VINCENZOFORNACIARI, WILLIAM +
Area compaction in Silicon Structures for Neural Net Implementation 1-gen-1990 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTEFANELLI, RENATOSTORTI GAJANI, GIANCARLO
Array partitioning: a methodology for reconfigurability and reconfiguration problems 1-gen-1988 DISTANTE, FAUSTOSCIUTO, DONATELLA +
DFGs for Synthesis of Alternatives Architectures: Node Activation Synthesis 1-gen-1992 ANTOLA, ANNA MARIADISTANTE, FAUSTO
Fault Tolerant Characteristics of the Linear Array Architecture for WSI Implementation of Neural Nets 1-gen-1991 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTEFANELLI, RENATOSTORTI GAJANI, GIANCARLO
Fault Tollerant Aspects in Silicon Structures for Neural Nets 1-gen-1989 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTEFANELLI, RENATOSTORTI GAJANI, GIANCARLO
High level architectural synthesis: precedence analysis ad automatic cycle detection 1-gen-1994 ANTOLA, ANNA MARIADISTANTE, FAUSTO +
High level synthesis through folding of data flow graphs: optimal intra-node scheduling 1-gen-1993 ANTOLA, ANNA MARIADISTANTE, FAUSTO +
Mapping Neural Nets onto Massively parallel Silicon Architectures: A Defect-Tolerance Solution 1-gen-1991 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTEFANELLI, RENATOSTORTI GAJANI, GIANCARLO
Multistage Interleaved Architectures for Implementation of Neural Networks 1-gen-1989 DISTANTE, FAUSTOSTORTI GAJANI, GIANCARLOSTEFANELLI, RENATOSAMI, MARIAGIOVANNA
Optimal Balancing of Acyclic and Cyclic Data Flow Graphs in High Level Architectural Synthesis 1-gen-1994 ANTOLA, ANNA MARIADISTANTE, FAUSTO