ZONI, DAVIDE

ZONI, DAVIDE  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Risultati 1 - 20 di 22 (tempo di esecuzione: 0.057 secondi).
Titolo Data di pubblicazione Autori File
All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores 1-gen-2020 Zoni, DavideCremona, LucaFornaciari, William
All-digital energy-constrained controller for general-purpose accelerators and CPUs 1-gen-2019 Davide ZoniLuca CremonaWilliam Fornaciari
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems 1-gen-2021 Luca CremonaWilliam FornaciariDavide Zoni
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers 1-gen-2017 Zoni, DavideCanidio, AndreaFornaciari, William +
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture 1-gen-2018 D. ZoniA. BarenghiG. PelosiW. Fornaciari
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties 1-gen-2017 PALERMO, GIANLUCAFORNACIARI, WILLIAMBRANDOLESE, CARLOGADIOLI, DAVIDEVITALI, EMANUELEZONI, DAVIDE +
A Control-based Methodology for Power-performance Optimization in NoCs Exploiting DVFS 1-gen-2015 Zoni, DavideTerraneo, FedericoFornaciari, William
Cost-effective fixed-point hardware support for RISC-V embedded systems 1-gen-2022 D. ZoniA. Galimberti
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-based NoCs 1-gen-2015 Zoni, DavideFornaciari, William +
DarkCache: Energy-performance Optimization of Tiled Multi-cores by Adaptively Power Gating LLC Banks 1-gen-2018 Davide ZoniWilliam Fornaciari +
Design of side-channel resistant power monitors 1-gen-2022 Zoni, DavideCremona, LucaFornaciari, William
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations 1-gen-2016 ZONI, DAVIDETERRANEO, FEDERICOFORNACIARI, WILLIAM
Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems 1-gen-2022 A. GalimbertiD. Zoni +
Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography 1-gen-2020 Davide ZoniAndrea GalimbertiWilliam Fornaciari
Exploring Manycore Architectures for Next-Generation HPC Systems through the MANGO Approach 1-gen-2018 Giovanni AgostaCarlo BrandoleseWilliam FornaciariSimone LibuttiGiuseppe MassariAnna PupykinaFederico ReghenzaniMichele ZanellaDavide Zoni +
Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials 1-gen-2020 Davide ZoniAndrea GalimbertiWilliam Fornaciari
An FPU design template to optimize the accuracy-efficiency-area trade-off 1-gen-2021 Davide ZoniAndrea GalimbertiWilliam Fornaciari
A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era 1-gen-2019 Davide Zoni +
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators 1-gen-2022 Davide Zoni +
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators 1-gen-2015 ZONI, DAVIDEFORNACIARI, WILLIAM