CASSANO, LUCA MARIA

CASSANO, LUCA MARIA  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Risultati 1 - 20 di 29 (tempo di esecuzione: 0.045 secondi).
Titolo Data di pubblicazione Autori File
A configurable board-level adaptive incremental diagnosis technique based on decision trees 1-gen-2015 BOLCHINI, CRISTIANACASSANO, LUCA MARIA
A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses 1-gen-2021 Cassano, LucaOttavi, Marco +
A Microprocessor Protection Architecture against Hardware Trojans in Memories 1-gen-2020 Cassano L.Ottavi M. +
A novel adaptive fault tolerant flip-flop architecture based on TMR 1-gen-2014 Cassano, Luca +
A Smart Fault Detection Scheme for Reliable Image Processing Applications 1-gen-2019 Matteo BiasielliCristiana BolchiniLuca CassanoAntonio Miele
An Approximation-based Fault Detection Scheme for Image Processing Applications 1-gen-2020 Biasielli M.Cassano L.Miele A.
An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems 1-gen-2014 Cassano, Luca +
Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs 1-gen-2014 Cassano, Luca +
Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications 1-gen-2023 Bolchini C.Cassano L.Miele A.Nazzari A.Passarello D.
Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses 1-gen-2023 Palumbo, AlessandroOttavi, MarcoCassano, Luca
Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope? 1-gen-2022 Bolchini C.Cassano L.Miele A. +
Early assessment of SEU sensitivity through untestable fault identification 1-gen-2014 Cassano, Luca +
Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs 1-gen-2020 Bolchini C.Cassano L.Mazzeo A.Miele A.
Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems 1-gen-2014 Cassano, Luca +
Formal approaches to SEU testing in FPGAs 1-gen-2013 Cassano, Luca +
HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems 1-gen-2019 Cristiana BolchiniLuca CassanoREPOLE, GIAMPIERO +
Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes 1-gen-2023 Palumbo, AlessandroCassano, LucaOttavi, Marco +
Is RISC-V ready for Space? A Security Perspective 1-gen-2022 Cassano, LucaPalumbo, Alessandro +
Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis 1-gen-2016 BOLCHINI, CRISTIANACASSANO, LUCA MARIAMIELE, ANTONIO ROSARIO
Lightweight Fault Detection and Management for Image Restoration 1-gen-2020 Bolchini C.Cassano L.Miele A. +