In the Ph.D. thesis1 from which this summary has been extracted the author proposed a framework of methodologies for the analysis and test of the effects of Single Event Upsets (SEUs) in the configuration memory of SRAM-based FPGA systems. In particular, an accurate SEU simulator for the early assessment of the sensitivity of SRAM-based FPGA systems to SEUs has been proposed, as well as a model-checking based untestability analysis methodology and a genetic algorithm-based automatic test pattern generation environment. All the proposed methodologies have been applied to a set of circuits from the ITC'99 benchmark and the SEU simulator has also been applied to the MiniMips microprocessor.

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

Cassano, Luca;
2014

Abstract

In the Ph.D. thesis1 from which this summary has been extracted the author proposed a framework of methodologies for the analysis and test of the effects of Single Event Upsets (SEUs) in the configuration memory of SRAM-based FPGA systems. In particular, an accurate SEU simulator for the early assessment of the sensitivity of SRAM-based FPGA systems to SEUs has been proposed, as well as a model-checking based untestability analysis methodology and a genetic algorithm-based automatic test pattern generation environment. All the proposed methodologies have been applied to a set of circuits from the ITC'99 benchmark and the SEU simulator has also been applied to the MiniMips microprocessor.
Proceedings - International Test Conference
9781479947225
Automatic Test Pattern Generation; Failure Probability; Fault Simulation; SEU Sensitivity; Single Event Upsets; SRAM-based FPGAs; Untestability Analysis; Applied Mathematics; Electrical and Electronic Engineering
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1043205
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