An inter-processor communication interface for data-flow centric heterogeneous embedded multiprocessor systems

Modern high-performance embedded systems are characterized by heterogeneity of the employed processing elements: general-purpose processors working together with embedded processors and with dedicated hardware accelerators or high-speed I/O interfaces. Communication among these processors and interfaces is one of the crucial aspects of the development of such systems. In this paper we present a communication interface for heterogeneous embedded multiprocessor systems. The interface is intended to be used to synchronize the data-flow between hardware accelerators and high-speed I/O interfaces. The interface has been designed with the aim of finding a trade-off between performance, flexibility and usability. In order to assess its performance and usability, the interface has been implemented and applied to a heterogeneous multiprocessor architecture used for payload processing in satellite systems. © 2014 IEEE.