It has been demonstrated that Software exploitable Hardware Trojan Horses (HTHs) can be inserted in commercial CPUs and memories. Such attacks allow malicious users to run their own software or to gain unauthorized privileges over the system. As a consequence, HTHs must nowadays be considered a serious threat not only from academy but also from industry. In this paper we present a security checking module meant to be connected between the microprocessor and the instruction memory in order to monitor the fetching activity with the aim of detecting the activation of HTHs. In particular, we aim at detecting those HTHs that alter the expected execution flow by launching a malicious program. We integrated the proposed security checking module within a case study system based on a RISC-V microprocessor implemented on an FPGA and running a set of software benchmarks. This experiment demonstrated that our proposal is able to detect 100% of possible HTHs activations with no false alarms. We measured a LUT overhead of 0.5% and a FF overhead of 0.3%, with a 2.36% power consumption increase and no working frequency reduction.

A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses

Cassano, Luca;Ottavi, Marco
2021-01-01

Abstract

It has been demonstrated that Software exploitable Hardware Trojan Horses (HTHs) can be inserted in commercial CPUs and memories. Such attacks allow malicious users to run their own software or to gain unauthorized privileges over the system. As a consequence, HTHs must nowadays be considered a serious threat not only from academy but also from industry. In this paper we present a security checking module meant to be connected between the microprocessor and the instruction memory in order to monitor the fetching activity with the aim of detecting the activation of HTHs. In particular, we aim at detecting those HTHs that alter the expected execution flow by launching a malicious program. We integrated the proposed security checking module within a case study system based on a RISC-V microprocessor implemented on an FPGA and running a set of software benchmarks. This experiment demonstrated that our proposal is able to detect 100% of possible HTHs activations with no false alarms. We measured a LUT overhead of 0.5% and a FF overhead of 0.3%, with a 2.36% power consumption increase and no working frequency reduction.
2021
2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
978-1-6654-1609-2
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1204477
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