Various formal approaches can be used to study FPGA-based systems in relationships to faults, in particular to SEUs. Formal approaches, such as high-order logic, model checking, or Stochastic Activity Networks, have been used for fault simulation, analysis of (un)testability, and test pattern generation. This paper reports on experiences and future developments related to soft errors in the configuration memory of SRAM-based devices, which are of particular interest for reconfigurable systems. © 2013 IEEE.

Formal approaches to SEU testing in FPGAs

Cassano, Luca;
2013

Abstract

Various formal approaches can be used to study FPGA-based systems in relationships to faults, in particular to SEUs. Formal approaches, such as high-order logic, model checking, or Stochastic Activity Networks, have been used for fault simulation, analysis of (un)testability, and test pattern generation. This paper reports on experiences and future developments related to soft errors in the configuration memory of SRAM-based devices, which are of particular interest for reconfigurable systems. © 2013 IEEE.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2013
9781467363839
Hardware and Architecture; Electrical and Electronic Engineering
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1043215
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