RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

PILATO, CHRISTIAN
 Distribuzione geografica
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Continente #
NA - Nord America 4.950
EU - Europa 1.423
AS - Asia 559
AF - Africa 14
SA - Sud America 10
Continente sconosciuto - Info sul continente non disponibili 4
OC - Oceania 3
Totale 6.963
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Nazione #
US - Stati Uniti d'America 4.889
IT - Italia 502
VN - Vietnam 163
UA - Ucraina 139
SE - Svezia 130
CN - Cina 126
DE - Germania 121
SG - Singapore 106
FI - Finlandia 98
GB - Regno Unito 94
IE - Irlanda 91
AT - Austria 59
CA - Canada 58
FR - Francia 43
ES - Italia 39
JO - Giordania 34
IN - India 31
KR - Corea 29
JP - Giappone 26
CH - Svizzera 24
PL - Polonia 20
HK - Hong Kong 17
NL - Olanda 16
BE - Belgio 13
RU - Federazione Russa 10
CI - Costa d'Avorio 8
TR - Turchia 8
IR - Iran 7
BR - Brasile 6
RO - Romania 6
ET - Etiopia 4
EU - Europa 4
GR - Grecia 4
EE - Estonia 3
ID - Indonesia 3
PT - Portogallo 3
TW - Taiwan 3
CO - Colombia 2
CR - Costa Rica 2
CZ - Repubblica Ceca 2
DK - Danimarca 2
MU - Mauritius 2
NZ - Nuova Zelanda 2
PK - Pakistan 2
SK - Slovacchia (Repubblica Slovacca) 2
AL - Albania 1
AU - Australia 1
AZ - Azerbaigian 1
BY - Bielorussia 1
CL - Cile 1
IL - Israele 1
MX - Messico 1
MY - Malesia 1
SA - Arabia Saudita 1
VE - Venezuela 1
Totale 6.963
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Città #
Fairfield 791
Woodbridge 545
Chandler 434
Ashburn 408
Houston 368
Wilmington 313
Seattle 310
Ann Arbor 283
Cambridge 271
Milan 127
Dong Ket 98
Dearborn 94
Lawrence 89
Dublin 83
Jacksonville 82
Singapore 59
Beijing 57
Medford 57
Vienna 56
Ottawa 50
San Diego 49
Redwood City 40
Málaga 37
Des Moines 35
Helsinki 35
Princeton 35
Amman 34
New York 32
Phoenix 24
Warsaw 20
Auburn Hills 18
Rome 15
Bern 13
Brussels 13
Seongnam 13
Boardman 11
Los Angeles 11
Paris 11
Takasago 11
Shanghai 10
Verona 10
Amsterdam 9
Washington 9
Abidjan 8
Miami 8
Dresden 7
Lappeenranta 7
London 7
Philadelphia 7
Bollate 6
Chicago 6
Columbus 6
Hefei 6
Mountain View 6
Norwalk 6
Richland 6
Seoul 6
Vimodrone 6
Central District 5
Kilburn 5
Shenzhen 5
Bari 4
Central 4
Dalian 4
Gainesville 4
Hong Kong 4
Monza 4
Nanjing 4
Pavia 4
Seveso 4
Tignale 4
Atlanta 3
Cassina Valsassina 3
Catanzaro 3
Cicero 3
Guangzhou 3
Islington 3
Jena 3
Melzo 3
Nanchang 3
Padova 3
Perugia 3
Portland 3
Redmond 3
Rūpnagar 3
San Donato Milanese 3
San Francisco 3
São Paulo 3
Tallinn 3
Véry 3
Xian 3
Arnesano 2
Bergamo 2
Berlin 2
Biassono 2
Boydton 2
Canzo 2
Collecchio 2
Colleferro 2
Como 2
Totale 5.301
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Nome #
A Survey and Evaluation of FPGA High-Level Synthesis Tools 201
An Evolutionary Approach to Area-Time Optimization of FPGA designs 161
Accelerator Design with High-Level Synthesis 143
CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching 140
The Case for Polymorphic Registers in Dataflow Computing 137
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 132
A framework for effective exploitation of partial reconfiguration in dataflow computing 128
D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems 126
The FASTER vision for designing dynamically reconfigurable systems 125
A Design Methodology for the Automatic Sizing of Standard-Cell Libraries 124
SMASH: A Heuristic Methodology for Designing Partially Reconfigurable MPSoCs 117
Black-Hat High-Level Synthesis: Myth or Reality? 114
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 111
A design methodology to implement memory accesses in High-Level Synthesis 111
A2B: an Integrated Framework for Designing Heterogeneous and Reconfigurable Systems 109
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance 108
Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis 108
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 106
Dataflow Computing with Polymorphic Registers 103
Is Register Transfer Level Locking Secure? 103
hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms 102
TaBit: A framework for task graph to bitstream generation 101
Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis 100
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells 100
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems 99
Bambu: A Modular Framework for the High Level Synthesis of Memory-Intensive Applications 99
An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs 98
A Runtime Adaptive Controller for Supporting Hardware Components with Variable Latency 97
Automatic Generation of Heterogeneous SoC Architectures with Secure Communications 96
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 94
The hArtes Tool Chain 92
Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration 91
Extensions of the hArtes Tool Chain 91
A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs 90
An open-source design and validation platform for reconfigurable systems 90
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis 89
Combined architecture and hardening techniques exploration for reliable embedded system design 87
In Car Audio 83
On the automatic integration of hardware accelerators into FPGA-based embedded systems 83
On the development of a runtime reconfigurable multicore system-on-chip 82
PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures 79
Performance Estimation of Task Graphs Based on Path Profiling 79
A SystemC-Based Framework for the Simulation of Appliances Networks in Energy-Aware Smart Spaces 77
Automatic run-time manager generation for reconfigurable MPSoC architectures 77
Smart technologies for effective reconfiguration: The FASTER approach 77
Improving Evolutionary Exploration to Area-Time Optimization of FPGA Designs 76
Performance Estimation for Task Graphs Combining Sequential Path Profiling and Control Dependence Regions 76
Runtime adaptation on dataflow HPC platforms 74
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration 74
Mapping and scheduling of parallel C applications with Ant Colony Optimization onto heterogeneous reconfigurable MPSoCs 74
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications 73
TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking 71
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip 70
CAD-Base: An Attack Vector into the Electronics Supply Chain 70
TAO: Techniques for algorithm-level obfuscation during high-level synthesis 67
Performance Modeling of Parallel Applications on MPSoCs 66
Scala-based domain-specific language for creating accelerator-based SoCs 66
Ant Colony Optimization for Mapping, Scheduling and Placing in Reconfigurable Systems 65
High-Level Synthesis of Benevolent Trojans 65
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems 63
HW/SW methodologies for synchronization in FPGA multiprocessors 61
FASTER: Facilitating analysis and synthesis technologies for effective reconfiguration 60
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip 59
Novel design methods and a tool flow for unleashing dynamic reconfiguration 59
DarkMem: Fine-grained power management of local memories for accelerators in embedded systems 57
A design methodology for compositional high-level synthesis of communication-centric SoCs 57
The hArtes CarLab: A New Approach to Advanced Algorithms Development for Automotive Audio 56
A Flexible and Reconfigurable Interconnection Structure for FPGA Dataflow Applications 54
System-level memory optimization for high-level synthesis of component-based SoCs 54
Effective reconfigurable design: The FASTER approach 53
EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms 50
On the design of scalable and reusable accelerators for big data applications 49
ASSURE: RTL Locking Against an Untrusted Foundry 48
SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels 47
A Survey of FPGA Optimization Methods for Data Center Energy Efficiency 45
The hArtes CarLab: A New Approach to Advanced Algorithms Development for Automotive Audio 45
Agile SoC Development with Open ESP : Invited Paper 40
From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics 40
Mapping pipelined applications onto heterogeneous embedded systems: a Bayesian Optimization Algorithm based approach 39
Compiler Infrastructure for Specializing Domain-Specific Memory Templates 34
Protecting Hardware IP Cores During High-Level Synthesis 33
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks 32
Securing Hardware Accelerators: A New Challenge for High-Level Synthesis 31
A Survey on Domain-Specific Memory Architectures 30
Evaluating Static CMOS Complex Cells in Technology Mapping 24
Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics 20
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis 20
Exploring eFPGA-based Redaction for IP Protection 19
Towards High-Level Synthesis of Quantum Circuits 18
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? 18
High-Level Synthesis of Security Properties via Software-Level Abstractions 14
Dynamically-Tunable Dataflow Architectures Based on Markov Queuing Models 14
Optimizing the Use of Behavioral Locking for High-Level Synthesis 12
Foundation Models in Augmentative and Alternative Communication: Opportunities and Challenges 11
Invited: High-level design methods for hardware security: Is it the right choice? 10
ALICE: An Automatic Design Flow for eFPGA Redaction 9
A Composable Design Space Exploration Framework to Optimize Behavioral Locking 9
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction 9
Generating Posit-Based Accelerators With High-Level Synthesis 8
Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization 7
Totale 7.165
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Categoria #
all - tutte 25.622
article - articoli 7.206
book - libri 0
conference - conferenze 16.704
curatela - curatele 42
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 1.630
Totale 51.204
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201.486 0 109 30 126 196 204 184 144 182 91 117 103
2020/2021971 78 71 75 75 72 50 37 75 97 76 84 181
2021/20221.125 42 140 148 41 169 51 80 86 54 45 111 158
2022/2023971 130 96 28 130 97 110 14 64 155 62 51 34
2023/2024682 32 96 86 62 34 77 45 73 15 48 13 101
2024/202518 9 9 0 0 0 0 0 0 0 0 0 0
Totale 7.195