RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

PILATO, CHRISTIAN
 Distribuzione geografica
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Continente #
NA - Nord America 5.389
EU - Europa 1.498
AS - Asia 709
SA - Sud America 31
AF - Africa 26
OC - Oceania 5
Continente sconosciuto - Info sul continente non disponibili 4
Totale 7.662
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Nazione #
US - Stati Uniti d'America 5.326
IT - Italia 527
SG - Singapore 173
VN - Vietnam 163
CN - Cina 139
UA - Ucraina 139
DE - Germania 135
SE - Svezia 131
FI - Finlandia 104
GB - Regno Unito 96
IE - Irlanda 91
ID - Indonesia 63
AT - Austria 59
CA - Canada 58
FR - Francia 43
ES - Italia 39
JO - Giordania 34
NL - Olanda 32
IN - India 31
KR - Corea 29
JP - Giappone 26
CH - Svizzera 24
BR - Brasile 23
PL - Polonia 23
HK - Hong Kong 20
BE - Belgio 13
RU - Federazione Russa 12
TR - Turchia 11
BJ - Benin 10
CI - Costa d'Avorio 8
IR - Iran 7
RO - Romania 7
EE - Estonia 4
ET - Etiopia 4
EU - Europa 4
GR - Grecia 4
AU - Australia 3
CR - Costa Rica 3
CZ - Repubblica Ceca 3
DK - Danimarca 3
PK - Pakistan 3
PT - Portogallo 3
TW - Taiwan 3
CL - Cile 2
CO - Colombia 2
MU - Mauritius 2
NZ - Nuova Zelanda 2
PH - Filippine 2
SK - Slovacchia (Repubblica Slovacca) 2
VE - Venezuela 2
AL - Albania 1
AR - Argentina 1
AZ - Azerbaigian 1
BY - Bielorussia 1
DZ - Algeria 1
EC - Ecuador 1
IL - Israele 1
JM - Giamaica 1
LU - Lussemburgo 1
LV - Lettonia 1
MX - Messico 1
MY - Malesia 1
SA - Arabia Saudita 1
UZ - Uzbekistan 1
ZA - Sudafrica 1
Totale 7.662
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Città #
Fairfield 791
Woodbridge 545
Chandler 434
Ashburn 408
Houston 368
Wilmington 313
Seattle 311
Santa Clara 309
Ann Arbor 283
Cambridge 271
Milan 142
Boardman 123
Singapore 107
Dong Ket 98
Dearborn 94
Lawrence 89
Dublin 83
Jacksonville 82
Jakarta 62
Beijing 58
Medford 57
Vienna 56
Ottawa 50
San Diego 49
Redwood City 40
Málaga 37
Des Moines 35
Helsinki 35
Princeton 35
Amman 34
New York 32
Amsterdam 24
Phoenix 24
Warsaw 20
Auburn Hills 18
Rome 15
Los Angeles 14
Bern 13
Brussels 13
Lappeenranta 13
Seongnam 13
Paris 11
Shanghai 11
Takasago 11
Cotonou 10
Verona 10
Washington 9
Abidjan 8
Dresden 8
Falkenstein 8
London 8
Miami 8
Philadelphia 7
Bollate 6
Chicago 6
Columbus 6
Hefei 6
Monza 6
Mountain View 6
Norwalk 6
Richland 6
Seoul 6
São Paulo 6
Vimodrone 6
Central District 5
Frankfurt am Main 5
Hong Kong 5
Istanbul 5
Kilburn 5
Shenzhen 5
Bari 4
Central 4
Cormano 4
Dalian 4
Gainesville 4
Nanjing 4
Pavia 4
Seveso 4
Tallinn 4
Tignale 4
Atlanta 3
Cassina Valsassina 3
Catanzaro 3
Cicero 3
Guangzhou 3
Islington 3
Jena 3
Melzo 3
Munich 3
Nanchang 3
Padova 3
Perugia 3
Portland 3
Redmond 3
Rūpnagar 3
San Donato Milanese 3
San Francisco 3
The Dalles 3
Véry 3
Xian 3
Totale 5.903
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Nome #
A Survey and Evaluation of FPGA High-Level Synthesis Tools 216
An Evolutionary Approach to Area-Time Optimization of FPGA designs 166
CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching 155
Accelerator Design with High-Level Synthesis 153
The Case for Polymorphic Registers in Dataflow Computing 142
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 140
D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems 136
A framework for effective exploitation of partial reconfiguration in dataflow computing 136
Extensions of the hArtes Tool Chain 130
The FASTER vision for designing dynamically reconfigurable systems 128
A Design Methodology for the Automatic Sizing of Standard-Cell Libraries 127
SMASH: A Heuristic Methodology for Designing Partially Reconfigurable MPSoCs 125
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance 118
Black-Hat High-Level Synthesis: Myth or Reality? 118
A2B: an Integrated Framework for Designing Heterogeneous and Reconfigurable Systems 117
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 116
A design methodology to implement memory accesses in High-Level Synthesis 116
Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis 113
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 112
TaBit: A framework for task graph to bitstream generation 110
Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis 109
Is Register Transfer Level Locking Secure? 108
Dataflow Computing with Polymorphic Registers 107
hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms 107
A Runtime Adaptive Controller for Supporting Hardware Components with Variable Latency 105
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 104
An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs 104
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells 104
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems 103
Automatic Generation of Heterogeneous SoC Architectures with Secure Communications 102
The hArtes Tool Chain 101
Bambu: A Modular Framework for the High Level Synthesis of Memory-Intensive Applications 101
An open-source design and validation platform for reconfigurable systems 99
Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration 99
A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs 95
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis 94
Combined architecture and hardening techniques exploration for reliable embedded system design 92
On the automatic integration of hardware accelerators into FPGA-based embedded systems 92
In Car Audio 90
On the development of a runtime reconfigurable multicore system-on-chip 90
PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures 86
Automatic run-time manager generation for reconfigurable MPSoC architectures 86
Performance Estimation of Task Graphs Based on Path Profiling 86
Smart technologies for effective reconfiguration: The FASTER approach 85
Improving Evolutionary Exploration to Area-Time Optimization of FPGA Designs 82
Performance Estimation for Task Graphs Combining Sequential Path Profiling and Control Dependence Regions 82
A SystemC-Based Framework for the Simulation of Appliances Networks in Energy-Aware Smart Spaces 82
Runtime adaptation on dataflow HPC platforms 81
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications 80
Mapping and scheduling of parallel C applications with Ant Colony Optimization onto heterogeneous reconfigurable MPSoCs 79
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration 77
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip 75
TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking 74
Performance Modeling of Parallel Applications on MPSoCs 73
Scala-based domain-specific language for creating accelerator-based SoCs 73
CAD-Base: An Attack Vector into the Electronics Supply Chain 73
Ant Colony Optimization for Mapping, Scheduling and Placing in Reconfigurable Systems 70
TAO: Techniques for algorithm-level obfuscation during high-level synthesis 70
High-Level Synthesis of Benevolent Trojans 68
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems 67
HW/SW methodologies for synchronization in FPGA multiprocessors 66
A Flexible and Reconfigurable Interconnection Structure for FPGA Dataflow Applications 65
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip 63
FASTER: Facilitating analysis and synthesis technologies for effective reconfiguration 62
A design methodology for compositional high-level synthesis of communication-centric SoCs 61
Novel design methods and a tool flow for unleashing dynamic reconfiguration 61
DarkMem: Fine-grained power management of local memories for accelerators in embedded systems 60
The hArtes CarLab: A New Approach to Advanced Algorithms Development for Automotive Audio 59
EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms 59
System-level memory optimization for high-level synthesis of component-based SoCs 58
On the design of scalable and reusable accelerators for big data applications 56
Effective reconfigurable design: The FASTER approach 55
ASSURE: RTL Locking Against an Untrusted Foundry 55
A Survey of FPGA Optimization Methods for Data Center Energy Efficiency 53
SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels 50
From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics 48
The hArtes CarLab: A New Approach to Advanced Algorithms Development for Automotive Audio 47
Mapping pipelined applications onto heterogeneous embedded systems: a Bayesian Optimization Algorithm based approach 43
Agile SoC Development with Open ESP : Invited Paper 43
Compiler Infrastructure for Specializing Domain-Specific Memory Templates 43
A Survey on Domain-Specific Memory Architectures 37
Protecting Hardware IP Cores During High-Level Synthesis 37
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks 35
Securing Hardware Accelerators: A New Challenge for High-Level Synthesis 34
Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics 31
Evaluating Static CMOS Complex Cells in Technology Mapping 26
Towards High-Level Synthesis of Quantum Circuits 25
Optimizing the Use of Behavioral Locking for High-Level Synthesis 25
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis 25
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? 23
Exploring eFPGA-based Redaction for IP Protection 22
High-Level Synthesis of Security Properties via Software-Level Abstractions 20
Dynamically-Tunable Dataflow Architectures Based on Markov Queuing Models 20
A Composable Design Space Exploration Framework to Optimize Behavioral Locking 18
ALICE: An Automatic Design Flow for eFPGA Redaction 17
Foundation Models in Augmentative and Alternative Communication: Opportunities and Challenges 16
Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization 16
Reconfigurable logic for hardware IP protection: Opportunities and challenges 14
Designing ML-resilient locking at register-transfer level 13
Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications 13
Totale 7.803
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Categoria #
all - tutte 30.003
article - articoli 8.488
book - libri 0
conference - conferenze 19.444
curatela - curatele 78
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 1.924
Totale 59.937
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020821 0 0 0 0 0 0 184 144 182 91 117 103
2020/2021971 78 71 75 75 72 50 37 75 97 76 84 181
2021/20221.125 42 140 148 41 169 51 80 86 54 45 111 158
2022/2023971 130 96 28 130 97 110 14 64 155 62 51 34
2023/2024682 32 96 86 62 34 77 45 73 15 48 13 101
2024/2025723 9 17 64 40 366 214 13 0 0 0 0 0
Totale 7.900