RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

PILATO, CHRISTIAN
 Distribuzione geografica
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Continente #
EU - Europa 9.662
NA - Nord America 8.869
AS - Asia 4.172
SA - Sud America 909
Continente sconosciuto - Info sul continente non disponibili 253
AF - Africa 151
OC - Oceania 13
Totale 24.029
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Nazione #
US - Stati Uniti d'America 8.669
SE - Svezia 5.700
RU - Federazione Russa 1.472
SG - Singapore 1.300
CN - Cina 1.233
IT - Italia 1.089
BR - Brasile 756
VN - Vietnam 582
KR - Corea 284
DE - Germania 217
FR - Francia 212
JP - Giappone 176
FI - Finlandia 164
GB - Regno Unito 163
UA - Ucraina 155
HK - Hong Kong 133
CA - Canada 117
IE - Irlanda 95
ID - Indonesia 90
AT - Austria 85
IN - India 77
NL - Olanda 70
ES - Italia 67
BD - Bangladesh 62
PL - Polonia 56
AR - Argentina 54
MA - Marocco 49
JO - Giordania 39
MX - Messico 34
ZA - Sudafrica 33
CH - Svizzera 31
TW - Taiwan 30
IQ - Iraq 27
TR - Turchia 26
PK - Pakistan 22
CI - Costa d'Avorio 20
EC - Ecuador 20
BE - Belgio 18
CL - Cile 18
CO - Colombia 17
VE - Venezuela 15
JM - Giamaica 14
SA - Arabia Saudita 13
PH - Filippine 11
RO - Romania 11
BJ - Benin 10
PT - Portogallo 10
PE - Perù 9
PY - Paraguay 9
CR - Costa Rica 8
KE - Kenya 8
UY - Uruguay 8
AU - Australia 7
IR - Iran 7
TN - Tunisia 7
UZ - Uzbekistan 7
AZ - Azerbaigian 6
DO - Repubblica Dominicana 6
EE - Estonia 6
ET - Etiopia 6
AE - Emirati Arabi Uniti 5
AL - Albania 5
DK - Danimarca 5
HN - Honduras 5
KG - Kirghizistan 5
MY - Malesia 5
NZ - Nuova Zelanda 5
TH - Thailandia 5
CZ - Repubblica Ceca 4
EG - Egitto 4
EU - Europa 4
GR - Grecia 4
TT - Trinidad e Tobago 4
BG - Bulgaria 3
DZ - Algeria 3
IL - Israele 3
KZ - Kazakistan 3
LB - Libano 3
NP - Nepal 3
PA - Panama 3
PS - Palestinian Territory 3
RS - Serbia 3
SK - Slovacchia (Repubblica Slovacca) 3
BA - Bosnia-Erzegovina 2
BH - Bahrain 2
BO - Bolivia 2
BS - Bahamas 2
CY - Cipro 2
GA - Gabon 2
GT - Guatemala 2
LV - Lettonia 2
MD - Moldavia 2
MU - Mauritius 2
NO - Norvegia 2
OM - Oman 2
SV - El Salvador 2
AG - Antigua e Barbuda 1
AO - Angola 1
BB - Barbados 1
BN - Brunei Darussalam 1
Totale 23.760
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Città #
Stockholm 5.568
Ashburn 1.280
Fairfield 791
Singapore 744
San Jose 592
Woodbridge 547
Milan 436
Chandler 434
Houston 380
Santa Clara 365
Wilmington 317
Seattle 316
Ann Arbor 285
Cambridge 272
Beijing 235
Council Bluffs 231
Seoul 230
The Dalles 210
Moscow 193
Hefei 171
Boardman 165
Tokyo 145
Ho Chi Minh City 129
Hanoi 118
Los Angeles 112
Lauterbourg 104
Hong Kong 103
Dong Ket 98
Dearborn 96
Lawrence 89
Dublin 87
Jacksonville 87
Helsinki 75
New York 75
North Charleston 70
São Paulo 69
Jakarta 66
Vienna 66
Rome 65
Medford 57
Dallas 54
San Diego 53
Buffalo 51
Ottawa 51
Warsaw 47
Las Vegas 42
Frankfurt am Main 41
Amsterdam 40
Redwood City 40
Amman 39
Málaga 37
Des Moines 36
London 36
Phoenix 36
Princeton 35
Kent 28
Atlanta 27
Chicago 27
Shanghai 27
Casablanca 25
Lappeenranta 25
Hangzhou 24
Orem 24
Haiphong 23
Rio de Janeiro 21
Salt Lake City 21
Brooklyn 20
Guangzhou 20
Nuremberg 20
Ulsan 20
Johannesburg 19
Taipei 19
Auburn Hills 18
Da Nang 18
Kenitra 18
Paris 18
Washington 18
Abidjan 17
Philadelphia 17
Columbus 16
Florence 16
Frisco 16
Bologna 15
Curitiba 15
Brussels 14
Mexico City 14
Miami 14
Montreal 14
Tianjin 14
Bern 13
Seongnam 13
Shenzhen 13
Verona 13
Nanjing 12
Belo Horizonte 11
Brasília 11
Campinas 11
Padova 11
Porto Alegre 11
Takasago 11
Totale 16.903
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Nome #
A Composable Design Space Exploration Framework to Optimize Behavioral Locking 2.008
Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications 1.987
HOLL: Program Synthesis for Higher Order Logic Locking 1.944
A Survey and Evaluation of FPGA High-Level Synthesis Tools 634
CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching 319
Accelerator Design with High-Level Synthesis 309
Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis 276
An Evolutionary Approach to Area-Time Optimization of FPGA designs 266
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 233
D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems 231
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications 229
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 226
Automatic Generation of Heterogeneous SoC Architectures with Secure Communications 222
A Design Methodology for the Automatic Sizing of Standard-Cell Libraries 221
A design methodology to implement memory accesses in High-Level Synthesis 218
A Runtime Adaptive Controller for Supporting Hardware Components with Variable Latency 213
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 210
TaBit: A framework for task graph to bitstream generation 206
A framework for effective exploitation of partial reconfiguration in dataflow computing 205
Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis 203
A2B: an Integrated Framework for Designing Heterogeneous and Reconfigurable Systems 202
Is Register Transfer Level Locking Secure? 202
Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration 200
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells 200
The Case for Polymorphic Registers in Dataflow Computing 199
Extensions of the hArtes Tool Chain 197
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance 195
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 194
A Survey of FPGA Optimization Methods for Data Center Energy Efficiency 190
SMASH: A Heuristic Methodology for Designing Partially Reconfigurable MPSoCs 190
Designing ML-resilient locking at register-transfer level 188
An open-source design and validation platform for reconfigurable systems 188
In Car Audio 187
Black-Hat High-Level Synthesis: Myth or Reality? 184
hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms 181
A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs 180
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip 179
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems 175
On the development of a runtime reconfigurable multicore system-on-chip 175
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis 174
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach 172
The FASTER vision for designing dynamically reconfigurable systems 172
Automatic run-time manager generation for reconfigurable MPSoC architectures 172
A SystemC-Based Framework for the Simulation of Appliances Networks in Energy-Aware Smart Spaces 170
Agile SoC Development with Open ESP : Invited Paper 170
The hArtes Tool Chain 168
On the automatic integration of hardware accelerators into FPGA-based embedded systems 168
ASSURE: RTL Locking Against an Untrusted Foundry 168
Smart technologies for effective reconfiguration: The FASTER approach 166
Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics 165
Performance Estimation for Task Graphs Combining Sequential Path Profiling and Control Dependence Regions 165
Runtime adaptation on dataflow HPC platforms 163
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems 163
Improving Evolutionary Exploration to Area-Time Optimization of FPGA Designs 160
A Flexible and Reconfigurable Interconnection Structure for FPGA Dataflow Applications 160
A design methodology for compositional high-level synthesis of communication-centric SoCs 158
Performance Modeling of Parallel Applications on MPSoCs 157
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? 157
Performance Estimation of Task Graphs Based on Path Profiling 157
An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs 156
Bambu: A Modular Framework for the High Level Synthesis of Memory-Intensive Applications 151
CAD-Base: An Attack Vector into the Electronics Supply Chain 151
Optimizing the Use of Behavioral Locking for High-Level Synthesis 150
PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures 150
Securing Hardware Accelerators: A New Challenge for High-Level Synthesis 150
ALICE: An Automatic Design Flow for eFPGA Redaction 149
Protecting Hardware IP Cores During High-Level Synthesis 149
Dataflow Computing with Polymorphic Registers 148
From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics 144
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis 141
Invited: High-level design methods for hardware security: Is it the right choice? 140
Reconfigurable logic for hardware IP protection: Opportunities and challenges 139
High-Level Synthesis of Benevolent Trojans 139
EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms 138
Combined architecture and hardening techniques exploration for reliable embedded system design 136
TaintHLS: High-Level Synthesis For Dynamic Information Flow Tracking 136
Using Static Analysis for Enhancing HLS Security 135
Ant Colony Optimization for Mapping, Scheduling and Placing in Reconfigurable Systems 135
DarkMem: Fine-grained power management of local memories for accelerators in embedded systems 135
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration 134
QHLS: An HLS Framework to Convert High-Level Descriptions to Quantum Circuits 131
Compiler Infrastructure for Specializing Domain-Specific Memory Templates 131
Towards High-Level Synthesis of Quantum Circuits 130
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip 128
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks 127
HW/SW methodologies for synchronization in FPGA multiprocessors 125
On the design of scalable and reusable accelerators for big data applications 125
A Survey on Domain-Specific Memory Architectures 125
Scala-based domain-specific language for creating accelerator-based SoCs 124
Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization 123
TAO: Techniques for algorithm-level obfuscation during high-level synthesis 121
Mapping and scheduling of parallel C applications with Ant Colony Optimization onto heterogeneous reconfigurable MPSoCs 115
Effective reconfigurable design: The FASTER approach 114
System-level memory optimization for high-level synthesis of component-based SoCs 114
Novel design methods and a tool flow for unleashing dynamic reconfiguration 114
Generating Posit-Based Accelerators With High-Level Synthesis 113
FASTER: Facilitating analysis and synthesis technologies for effective reconfiguration 112
The hArtes CarLab: A New Approach to Advanced Algorithms Development for Automotive Audio 110
Exploring eFPGA-based Redaction for IP Protection 109
Dynamically-Tunable Dataflow Architectures Based on Markov Queuing Models 109
Totale 22.677
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Categoria #
all - tutte 59.403
article - articoli 17.364
book - libri 0
conference - conferenze 38.234
curatela - curatele 274
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 3.266
Totale 118.541
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20221.083 0 140 148 41 169 51 80 86 54 45 111 158
2022/2023971 130 96 28 130 97 110 14 64 155 62 51 34
2023/2024682 32 96 86 62 34 77 45 73 15 48 13 101
2024/20252.170 9 17 64 40 366 214 161 182 317 146 300 354
2025/202614.298 1.157 1.381 505 720 457 474 1.120 500 6.198 888 287 611
2026/2027384 321 63 0 0 0 0 0 0 0 0 0 0
Totale 24.029