RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

SAMI, MARIAGIOVANNA

SAMI, MARIAGIOVANNA  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Risultati 1 - 20 di 46 (tempo di esecuzione: 0.079 secondi).
Titolo Data di pubblicazione Autori File
A Compact and Fast Silicon Implementation for Layered Neural Nets 1-gen-1990 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTORTI GAJANI, GIANCARLO +
A configurable array architecture for WSI implementation of neural nets 1-gen-1990 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTORTI GAJANI, GIANCARLO +
A DAG-based Design Approach for Reconfigugrable VLIW Processors 1-gen-1999 ALIPPI, CESAREFORNACIARI, WILLIAMSAMI, MARIAGIOVANNA +
A general configurable architecture for WSI implementation for neural nets 1-gen-1990 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTORTI GAJANI, GIANCARLO
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems 1-gen-2003 SAMI, MARIAGIOVANNASCIUTO, DONATELLASILVANO, CRISTINAZACCARIA, VITTORIO +
A Proposal for Neural Macrocell Array 1-gen-1990 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTORTI GAJANI, GIANCARLO +
A semi-custom approach for digital implementation of neural networks 1-gen-1991 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTORTI GAJANI, GIANCARLO +
ADSC: Application-Driven Storage Control for Energy Efficiency 1-gen-2011 CAPPIELLO, CINZIAPERNICI, BARBARASAMI, MARIAGIOVANNA +
Alternative Approaches for Mapping Neural Networks onto Silicon 1-gen-1989 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTEFANELLI, RENATOSTORTI GAJANI, GIANCARLO
An Approach for Digital Neural Network Design 1-gen-1991 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTEFANELLI, RENATOSTORTI GAJANI, GIANCARLO
An Array Architecture for WSI Implementation of Neural Nets 1-gen-1990 DISTANTE, FAUSTOSAMI, MARIAGIOVANNASTEFANELLI, RENATOSTORTI GAJANI, GIANCARLO
An instruction-level methodology for power estimation and optimization of embedded VLIW cores 1-gen-2002 SAMI, MARIAGIOVANNASCIUTO, DONATELLASILVANO, CRISTINAZACCARIA, VITTORIO +
Analyzing the Sensitivity to Faults of Synchronization Primitives 1-gen-2011 GRASSI, PAOLO ROBERTOSAMI, MARIAGIOVANNASPEZIALE, ETTORETARTARA, MICHELE
Behavioral Testability and Test Pattern Generation of the Hopfield Network Model 1-gen-1994 ALIPPI, CESARESAMI, MARIAGIOVANNASCIUTO, DONATELLA +
Branch Prediction Techniques for Low-Power VLIW Processors 1-gen-2003 PALERMO, GIANLUCASAMI, MARIAGIOVANNASILVANO, CRISTINAZACCARIA, VITTORIO +
Creating an Embedded Systems Program from Scratch: Nine years of experience at ALaRI 1-gen-2009 SAMI, MARIAGIOVANNA +
Design of Fault Tolerant Network Interfaces for NoCs 1-gen-2011 SAMI, MARIAGIOVANNA +
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW 1-gen-2000 ALIPPI, CESAREFORNACIARI, WILLIAMSAMI, MARIAGIOVANNA
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs 1-gen-2001 ALIPPI, CESAREFORNACIARI, WILLIAMSAMI, MARIAGIOVANNA +
Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering 1-gen-2002 SAMI, MARIAGIOVANNASCIUTO, DONATELLASILVANO, CRISTINAZACCARIA, VITTORIO +