Considers reconfigurable computing for application-specific systems, with particular reference to mixed-technology chips. A VLIW "core" is augmented by means of reconfigurable functional units (RFUs) and register files implemented via FPGA on to the same chip. The application is analyzed to extract segments of computation that could be usefully collapsed into complex instructions decoded and executed by the RFUs. In this paper, we focus on the problem of selecting the optimum extension to the native instruction set by means of the "best" segments of the computation that will become complex instructions. In particular, a genetic algorithm approach is introduced to analyze the population of candidates; modifications to the classic genetic operators are introduced to take into account the peculiarity of our problem. Applying the proposed methodology to some significant applications has validated the overall approach.

Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs

ALIPPI, CESARE;FORNACIARI, WILLIAM;SAMI, MARIAGIOVANNA
2001-01-01

Abstract

Considers reconfigurable computing for application-specific systems, with particular reference to mixed-technology chips. A VLIW "core" is augmented by means of reconfigurable functional units (RFUs) and register files implemented via FPGA on to the same chip. The application is analyzed to extract segments of computation that could be usefully collapsed into complex instructions decoded and executed by the RFUs. In this paper, we focus on the problem of selecting the optimum extension to the native instruction set by means of the "best" segments of the computation that will become complex instructions. In particular, a genetic algorithm approach is introduced to analyze the population of candidates; modifications to the classic genetic operators are introduced to take into account the peculiarity of our problem. Applying the proposed methodology to some significant applications has validated the overall approach.
2001
Rapid System Prototyping, 12th International Workshop on, 2001.
0-7695-1206-2
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/258807
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