RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

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About the performances of the advanced encryption standard in embedded systems with cache memory 1-gen-2003 BERTONI, GUIDO MARCOBREVEGLIERI, LUCA ODDONEFRAGNETO, PASQUALINAMACCHETTI, MARCOZACCARIA, VITTORIO +
Power-Performance System-Level Exploration of a MicroSPARC2-based Embedded Architecture 1-gen-2003 PALERMO, GIANLUCASILVANO, CRISTINAZACCARIA, VITTORIO
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 1-gen-2004 ZACCARIA, VITTORIO +
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip 1-gen-2004 ZACCARIA, VITTORIO +
Low Effort, High Accuracy Network-on-Chip Power Macro ModelingIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 1-gen-2004 ZACCARIA, VITTORIO +
Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors 1-gen-2004 PALERMO, GIANLUCASAMI, MARIAGIOVANNASILVANO, CRISTINAZACCARIA, VITTORIO +
Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach 1-gen-2005 PALERMO, GIANLUCASAMI, MARIAGIOVANNASILVANO, CRISTINAZACCARIA, VITTORIO +
Multi-Objective Design Space Exploration of Embedded Systems 1-gen-2005 PALERMO, GIANLUCASILVANO, CRISTINAZACCARIA, VITTORIO
Processor Architecture 1-gen-2005 SAMI, MARIAGIOVANNASCIUTO, DONATELLASILVANO, CRISTINAZACCARIA, VITTORIO +
Reducing the complexity of instruction-level power models for VLIW processors 1-gen-2005 SILVANO, CRISTINASAMI, MARIAGIOVANNASCIUTO, DONATELLAZACCARIA, VITTORIO +
AES power attack based on induced cache miss and countermeasure 1-gen-2005 BERTONI, GUIDO MARCOBREVEGLIERI, LUCA ODDONEMONCHIERO, MATTEOPALERMO, GIANLUCAZACCARIA, VITTORIO
A power attack methodology to AES based on induced cache misses: procedure, evaluation and possible countermeasures 1-gen-2006 BERTONI, GUIDO MARCOBREVEGLIERI, LUCA ODDONEMONCHIERO, MATTEOPALERMO, GIANLUCAZACCARIA, VITTORIO
Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product 1-gen-2007 ZACCARIA, VITTORIO +
An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks 1-gen-2008 PALERMO, GIANLUCASILVANO, CRISTINAZACCARIA, VITTORIO +
Robust Optimization of SoC Architectures: A Multi-Scenario Approach 1-gen-2008 PALERMO, GIANLUCASILVANO, CRISTINAZACCARIA, VITTORIO
Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration 1-gen-2008 PALERMO, GIANLUCASILVANO, CRISTINAZACCARIA, VITTORIO
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods 1-gen-2008 PALERMO, GIANLUCASILVANO, CRISTINAZACCARIA, VITTORIO
An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints 1-gen-2008 PALERMO, GIANLUCASILVANO, CRISTINAZACCARIA, VITTORIO
Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips 1-gen-2009 PALERMO, GIANLUCASILVANO, CRISTINAZACCARIA, VITTORIO +
A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip 1-gen-2009 PALERMO, GIANLUCASILVANO, CRISTINAZACCARIA, VITTORIO +
Mostrati risultati da 21 a 40 di 99
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