KARMAN, SALEH
 Distribuzione geografica
Continente #
NA - Nord America 436
EU - Europa 227
AS - Asia 47
OC - Oceania 2
AF - Africa 1
Totale 713
Nazione #
US - Stati Uniti d'America 430
IT - Italia 121
AT - Austria 21
DE - Germania 16
ES - Italia 11
SE - Svezia 10
JO - Giordania 9
VN - Vietnam 9
GB - Regno Unito 8
IE - Irlanda 8
FI - Finlandia 7
BE - Belgio 6
CA - Canada 6
CN - Cina 6
FR - Francia 6
IN - India 6
HK - Hong Kong 5
GR - Grecia 4
TW - Taiwan 4
JP - Giappone 3
SG - Singapore 3
UA - Ucraina 3
KR - Corea 2
AU - Australia 1
CH - Svizzera 1
EE - Estonia 1
EG - Egitto 1
LI - Liechtenstein 1
MK - Macedonia 1
NZ - Nuova Zelanda 1
PL - Polonia 1
RO - Romania 1
Totale 713
Città #
Chandler 85
Milan 49
Fairfield 44
Ashburn 39
Seattle 30
Woodbridge 25
Houston 23
Redmond 22
Ann Arbor 21
Vienna 20
Wilmington 20
Cambridge 16
Málaga 11
Amman 9
Lawrence 8
Medford 8
Dublin 7
San Diego 7
Brussels 6
Ottawa 6
Helsinki 5
Redwood City 5
Turin 5
Washington 5
Beijing 4
Central District 4
Athens 3
Dong Ket 3
Grafing 3
Legnano 3
London 3
Taipei 3
Berlin 2
Chicago 2
Columbus 2
Como 2
Dallas 2
Duncan 2
Edinburgh 2
Lappeenranta 2
Mauleon 2
Mondragone 2
New York 2
San Giuliano Milanese 2
San Mateo 2
Santa Clara 2
St Louis 2
Tokyo 2
Varese 2
Verdello 2
Auckland 1
Basiliano 1
Bucharest 1
Castrop-rauxel 1
Central 1
Chennai 1
Davis 1
Dearborn 1
Gdynia 1
Hounslow 1
Kilburn 1
Kyiv 1
Laguna Niguel 1
Lake Forest 1
Manchester 1
Monte Di Procida 1
Nagold 1
Nardò 1
New Ross 1
Norwalk 1
Paris 1
Patras 1
Pordenone 1
San Jose 1
Schaan 1
Shanghai 1
Sherman 1
Singapore 1
Stockholm 1
Sydney 1
Tallinn 1
Totale 569
Nome #
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 153
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 114
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 112
Single-resonator, time-switched FM MEMS accelerometer with theoretical offset drift complete cancellation 90
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 89
A Novel Topology of Coupled Phase-Locked Loops 62
Jitter Minimization in Digital PLLs with Mid-Rise TDCs 49
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability 35
SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends 24
Totale 728
Categoria #
all - tutte 2.582
article - articoli 1.187
book - libri 0
conference - conferenze 1.395
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 5.164


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/201930 0 0 0 0 0 0 0 0 0 0 16 14
2019/2020128 8 3 2 18 21 13 10 13 11 9 14 6
2020/2021113 8 9 7 13 7 1 0 11 14 15 9 19
2021/2022157 13 9 4 26 15 4 7 15 31 4 17 12
2022/2023214 20 22 6 38 20 23 2 10 34 17 21 1
2023/202477 11 8 11 5 7 11 4 2 3 15 0 0
Totale 728