statistiche ricercatore

Nazione	#
IT - Italia	85
US - Stati Uniti d'America	45
SG - Singapore	14
CN - Cina	10
KR - Corea	10
AT - Austria	5
FI - Finlandia	5
BJ - Benin	4
IE - Irlanda	4
IN - India	4
JP - Giappone	4
FR - Francia	3
TW - Taiwan	3
AZ - Azerbaigian	2
BE - Belgio	2
CA - Canada	2
ES - Italia	2
NL - Olanda	2
BR - Brasile	1
CH - Svizzera	1
DE - Germania	1
MO - Macao, regione amministrativa speciale della Cina	1
NO - Norvegia	1
VN - Vietnam	1
Totale	212

Nome	#
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering	59
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology	43
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM	31
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering	26
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique	23
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC	13
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion	12
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector	7
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars	6
A Low-Jitter Fractional-$N$ Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC	3
Totale	223

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2022/2023	30	0	0	0	0	0	0	0	0	15	7	4	4
2023/2024	68	1	9	3	2	6	3	13	11	6	1	4	9
2024/2025	125	18	10	39	28	30	0	0	0	0	0	0	0
Totale													223

RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano