NATALE, GIUSEPPE

NATALE, GIUSEPPE  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

Mostra records
Risultati 1 - 9 di 9 (tempo di esecuzione: 0.03 secondi).
Titolo Data di pubblicazione Autori File
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project 1-gen-2017 RABOZZI, MARCOBRONDOLIN, ROLANDONATALE, GIUSEPPEDEL SOZZO, EMANUELESANTAMBROGIO, MARCO DOMENICO +
A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains 1-gen-2017 Pappalardo, AlessandroNatale, GiuseppeSantambrogio, Marco Domenico
A framework with cloud integration for CNN acceleration on FPGA devices 1-gen-2018 RASPA, NICCOLO'Natale, GiuseppeBacis, MarcoSantambrogio, Marco D.
A pipelined and scalable dataflow implementation of convolutional neural networks on FPGA 1-gen-2017 BACIS, MARCONATALE, GIUSEPPEDEL SOZZO, EMANUELESANTAMBROGIO, MARCO DOMENICO
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops 1-gen-2016 NATALE, GIUSEPPESTRAMONDO, GIULIOCATTANEO, RICCARDOSCIUTO, DONATELLASANTAMBROGIO, MARCO DOMENICO +
An FPGA-based acceleration methodology and performance model for iterative stencils 1-gen-2018 Reggiani, EnricoNatale, GiuseppeSantambrogio, Marco D. +
Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project 1-gen-2017 RABOZZI, MARCONATALE, GIUSEPPEDEL SOZZO, EMANUELESCOLARI, ALBERTOSTORNAIUOLO, LUCASANTAMBROGIO, MARCO DOMENICO
On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks 1-gen-2017 NATALE, GIUSEPPEBACIS, MARCOSANTAMBROGIO, MARCO DOMENICO
Optimizing streaming stencil time-step designs via FPGA floorplanning 1-gen-2017 Rabozzi, MarcoNatale, GiuseppeFESTA, BIAGIOMiele, AntonioSantambrogio, Marco D.