In this work, we present a modular software subsystem that exposes a set of APIs for supporting the automation of a set of design choices in the synthesis of a hardware accelerator by a proprietary FPGA toolchain. We model the subsystem around Vivado, Xilinx's proprietary FPGA toolchain, in order to provide a finer grained control on the toolchain's features with respect to the standard.tcl interface. In order to do so, we focus on parsing the synthesis process' output as it happens, on automatically managing the toolchain's execution lifecycle, and on generating appropriate input.tcl scripts to interact with the standard APIs. On top of this subsystem, we extend polyFPGA, a framework for the FPGA acceleration of Iterative Stencil Loops (ISLs) that relies on Vivado. polyFPGA adopts the polyhedral model as a way to map a piece of input code to a queue of computational units, the Streaming Stencil Time-steps (SSTs), deployed on the target system. We show how the presented software subsystem allows the automation of the design space exploration (DSE) of a set of the synthesized architecture's hyperparameters, such as the queue's length and architecture's frequency, in a feedback based fashion, thanks on the information coming from the synthesis process and a set of user defined policies.

A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains

Pappalardo, Alessandro;Natale, Giuseppe;Santambrogio, Marco Domenico
2017

Abstract

In this work, we present a modular software subsystem that exposes a set of APIs for supporting the automation of a set of design choices in the synthesis of a hardware accelerator by a proprietary FPGA toolchain. We model the subsystem around Vivado, Xilinx's proprietary FPGA toolchain, in order to provide a finer grained control on the toolchain's features with respect to the standard.tcl interface. In order to do so, we focus on parsing the synthesis process' output as it happens, on automatically managing the toolchain's execution lifecycle, and on generating appropriate input.tcl scripts to interact with the standard APIs. On top of this subsystem, we extend polyFPGA, a framework for the FPGA acceleration of Iterative Stencil Loops (ISLs) that relies on Vivado. polyFPGA adopts the polyhedral model as a way to map a piece of input code to a queue of computational units, the Streaming Stencil Time-steps (SSTs), deployed on the target system. We show how the presented software subsystem allows the automation of the design space exploration (DSE) of a set of the synthesized architecture's hyperparameters, such as the queue's length and architecture's frequency, in a feedback based fashion, thanks on the information coming from the synthesis process and a set of user defined policies.
Proceedings - 20th Euromicro Conference on Digital System Design, DSD 2017
9781538621455
Dataflow Architectures; Design Space Exploration; Field Programmable Gate Arrays; Computer Science Applications1707 Computer Vision and Pattern Recognition; Control and Systems Engineering; Hardware and Architecture
File in questo prodotto:
File Dimensione Formato  
PID4861763.pdf

Accesso riservato

: Post-Print (DRAFT o Author’s Accepted Manuscript-AAM)
Dimensione 129.44 kB
Formato Adobe PDF
129.44 kB Adobe PDF   Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1041402
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 0
  • ???jsp.display-item.citation.isi??? 0
social impact