First Study of Bubble Error Artifacts in Field-Programmable Gate Array (FPGA)-Based Tapped Delay-Line Time-to-Digital Converters with Sum-of-Ones Decoder on Xilinx 28 nm 7-Series FPGA

Time-to-Digital Converters (TDCs) are increasingly vital in modern measurement systems, with Field-Programmable Gate Arrays (FPGAs) offering a cost-effective platform despite challenges in asynchronous circuit design. Among various solutions, Tapped Delay-Line (TDL)-TDCs stand out for balancing precision, speed, and resource efficiency. However, a primary concern in FPGA-based TDL-TDCs are the Bubble Errors (BEs), i.e., spurious zeros introduced in the information code in the TDL that put the measurement precision at severe risk. The main goal of this contribution is to investigate the distribution of BEs, utilizing the Clock Region Crossing (CRC) within the FPGA as a case study, in order to demonstrate theoretically and experimentally that if BEs are manipulated properly, they create an interpolation effect that reduces the quantization error of the TDL-TDC. The analysis is carried out on a 256-tap fully integrated TDL-TDC implemented in a 28 nm Xilinx Artix 100T FPGA. The outcome confirms the potential to use CRC-BEs instead of suppressing them with precision increasing up to 0.17 ps r.m.s., or by almost 2% while also supporting the correctness of the model.