BONANNO, GABRIELE

BONANNO, GABRIELE  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Risultati 1 - 9 di 9 (tempo di esecuzione: 0.015 secondi).
Titolo Data di pubblicazione Autori File
A Comparison of Voltage-Mode and Time-Based Timing and Energy Read-Out Circuits 1-gen-2023 Lusardi, N.Garzetti, F.Ronconi, E.Costa, A.Bonanno, G.Geraci, A. +
Design and Implementation of a High-Performance FPGA-bases Digital Instrument for Multi-Channel Time Measurements 1-gen-2023 Garzetti, F.Lusardi, N.Costa, A.Ronconi, E.Bonanno, G.Geraci, A.
Fully FPGA-based Compact Pulse-Width-Modulated Tunable Threshold Comparator Circuit for Time-to-Digital Converters 1-gen-2023 Costa, A.Ronconi, E.Garzetti, F.Lusardi, N.Bonanno, G.Geraci, A.
High Spatial Resolution Detector System Based on Reconfigurable Dual-FPGA Approach for Coincidence Measurements 1-gen-2024 Garzetti, FabioLusardi, NicolaCosta, AndreaBonanno, GabrieleRonconi, EnricoGeraci, Angelo +
High-Precision Digital-to-Time Converter with High Dynamic Range for 28 nm 7-Series Xilinx FPGA and SoC Devices 1-gen-2024 Garzetti, FabioLusardi, NicolaCorna, NicolaFiumicelli, GabrieleBonanno, GabrieleCosta, AndreaRonconi, EnricoGeraci, Angelo +
High-Rate Handling Solution for Multiple Channels, FPGA-Based, Time-to-Digital Converters 1-gen-2022 Garzetti, F.Costa, A.Ronconi, E.Lusardi, N.Corna, N.Bonanno, G.Geraci, A.
New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters 1-gen-2024 Garzetti, FabioBonanno, GabrieleLusardi, NicolaRonconi, EnricoCosta, AndreaGeraci, Angelo
Optimal Implementation of Tapped Delay Line Time-to-Digital Converters in 20 nm Xilinx UltraScale FPGAs 1-gen-2024 Lusardi, NicolaGarzetti, FabioFiumicelli, GabrieleBonanno, GabrieleRonconi, EnricoCosta, AndreaGeraci, Angelo +
Scalable Time Measurement System based on a Multi-FPGA Architecture 1-gen-2023 Ronconi, E.Costa, A.Lusardi, N.Garzetti, F.Bonanno, G.Fiumicelli, G.Deren, M.Geraci, A.