NATALE, GIUSEPPE
 Distribuzione geografica
Continente #
NA - Nord America 789
EU - Europa 201
AS - Asia 56
Totale 1.046
Nazione #
US - Stati Uniti d'America 783
AT - Austria 50
IT - Italia 49
VN - Vietnam 24
CN - Cina 22
ES - Italia 20
DE - Germania 17
FI - Finlandia 16
IE - Irlanda 12
GB - Regno Unito 9
SE - Svezia 8
UA - Ucraina 8
CA - Canada 6
GR - Grecia 6
HK - Hong Kong 3
JO - Giordania 3
BE - Belgio 2
CH - Svizzera 2
IN - India 2
JP - Giappone 1
NL - Olanda 1
RU - Federazione Russa 1
SG - Singapore 1
Totale 1.046
Città #
Fairfield 132
Woodbridge 107
Chandler 93
Ashburn 73
Seattle 54
Vienna 49
Houston 46
Wilmington 44
Cambridge 41
Ann Arbor 24
Málaga 20
Dong Ket 14
Helsinki 14
Dearborn 12
Medford 12
Dublin 11
Lawrence 11
Beijing 7
Redmond 6
Milan 5
Grazzano Badoglio 4
Ottawa 4
Redwood City 4
Shanghai 4
Amman 3
Columbus 3
London 3
Nanjing 3
Norwalk 3
Washington 3
Bern 2
Brussels 2
Hong Kong 2
Longueuil 2
Noale 2
Opera 2
San Diego 2
Wuhan 2
Absecon 1
Alghero 1
Aversa 1
Berlin 1
Boardman 1
Camarillo 1
Central 1
Changsha 1
Chicago 1
Chiswick 1
Cupertino 1
Des Moines 1
Florence 1
Frankfurt am Main 1
Groningen 1
Guangzhou 1
Guntur 1
Hefei 1
Jinan 1
Lamezia Terme 1
Los Angeles 1
Lviv 1
Miami 1
Moscow 1
Mountain View 1
Napoli 1
Nova Milanese 1
Robbiate 1
Rome 1
Southwark 1
Taiyuan 1
Tokyo 1
Worthing 1
Totale 858
Nome #
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project 124
Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project 109
Optimizing streaming stencil time-step designs via FPGA floorplanning 108
A pipelined and scalable dataflow implementation of convolutional neural networks on FPGA 105
A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains 95
An FPGA-based acceleration methodology and performance model for iterative stencils 94
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops 89
On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks 81
A framework with cloud integration for CNN acceleration on FPGA devices 78
On how to accelerate iterative stencil loops: A scalable streaming-based approach 74
Enabling Transparent Hardware Acceleration on Zynq SoC for Scientific Computing 61
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components 44
Totale 1.062
Categoria #
all - tutte 3.434
article - articoli 786
book - libri 0
conference - conferenze 2.648
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 6.868


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/2019107 0 0 0 0 0 0 0 0 0 28 41 38
2019/2020229 18 18 4 19 32 28 25 24 24 21 9 7
2020/2021166 10 12 28 12 8 8 5 14 11 23 8 27
2021/202297 5 14 4 6 10 4 2 11 5 9 12 15
2022/2023241 25 32 8 20 27 34 3 17 27 27 19 2
2023/202475 4 12 11 15 5 16 3 4 1 4 0 0
Totale 1.062