NATALE, GIUSEPPE
 Distribuzione geografica
Continente #
NA - Nord America 833
EU - Europa 216
AS - Asia 91
Totale 1.140
Nazione #
US - Stati Uniti d'America 827
IT - Italia 60
AT - Austria 50
SG - Singapore 35
VN - Vietnam 24
CN - Cina 23
ES - Italia 20
DE - Germania 19
FI - Finlandia 16
IE - Irlanda 12
GB - Regno Unito 9
SE - Svezia 8
UA - Ucraina 8
CA - Canada 6
GR - Grecia 6
HK - Hong Kong 3
JO - Giordania 3
BE - Belgio 2
CH - Svizzera 2
IN - India 2
NL - Olanda 2
BG - Bulgaria 1
JP - Giappone 1
RU - Federazione Russa 1
Totale 1.140
Città #
Fairfield 132
Woodbridge 107
Chandler 93
Ashburn 73
Seattle 54
Vienna 49
Houston 46
Wilmington 44
Cambridge 41
Santa Clara 30
Singapore 27
Ann Arbor 24
Málaga 20
Dong Ket 14
Helsinki 14
Boardman 13
Dearborn 12
Medford 12
Dublin 11
Lawrence 11
Beijing 7
Milan 7
Redmond 6
Brescia 5
Grazzano Badoglio 4
Ottawa 4
Redwood City 4
Shanghai 4
Amman 3
Columbus 3
London 3
Nanjing 3
Norwalk 3
Washington 3
Bern 2
Bologna 2
Brussels 2
Frankfurt am Main 2
Guangzhou 2
Hong Kong 2
Longueuil 2
Noale 2
Opera 2
San Diego 2
Wuhan 2
Absecon 1
Alghero 1
Amsterdam 1
Aversa 1
Berlin 1
Camarillo 1
Central 1
Changsha 1
Chicago 1
Chiswick 1
Cupertino 1
Des Moines 1
Florence 1
Groningen 1
Guntur 1
Hefei 1
Jinan 1
Karlsruhe 1
Lamezia Terme 1
Los Angeles 1
Lviv 1
Miami 1
Moscow 1
Mountain View 1
Napoli 1
Nova Milanese 1
Robbiate 1
Rome 1
Southwark 1
Taiyuan 1
The Dalles 1
Tokyo 1
Worthing 1
Totale 941
Nome #
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project 130
Optimizing streaming stencil time-step designs via FPGA floorplanning 118
Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project 117
A pipelined and scalable dataflow implementation of convolutional neural networks on FPGA 112
A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains 102
An FPGA-based acceleration methodology and performance model for iterative stencils 102
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops 95
On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks 89
A framework with cloud integration for CNN acceleration on FPGA devices 85
On how to accelerate iterative stencil loops: A scalable streaming-based approach 80
Enabling Transparent Hardware Acceleration on Zynq SoC for Scientific Computing 72
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components 54
Totale 1.156
Categoria #
all - tutte 4.236
article - articoli 1.015
book - libri 0
conference - conferenze 3.221
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 8.472


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020170 0 0 0 0 32 28 25 24 24 21 9 7
2020/2021166 10 12 28 12 8 8 5 14 11 23 8 27
2021/202297 5 14 4 6 10 4 2 11 5 9 12 15
2022/2023241 25 32 8 20 27 34 3 17 27 27 19 2
2023/202492 4 12 11 15 5 16 3 4 1 6 6 9
2024/202577 3 5 10 6 53 0 0 0 0 0 0 0
Totale 1.156